A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller

Abstract

A 4266Mb/s/pin LPDDR4 interface with an asynchronous feedback continuous-time linear equalizer (AF-CTLE) and an adaptive 3-step eye detection algorithm for memory controller is presented. The AF-CTLE removes the glitch of DQS without training by applying an offset larger than the noise, and improves read margin by operating as a decision feedback equalizer in DQ path. The adaptive 3-step eye detection algorithm reduces power consumption and black-out time in initialization sequence and retraining in comparison to the 2-D full scanning. A prototype chip was implemented in a 65-nm CMOS process with fine-pitch ball grid array package and tested with commodity LPDDR4 memory. The write margin was 0.36 UI and 148 mV; and the read margin was enhanced from 0.30 UI and 76 mV without AF-CTLE to 0.47 UI and 80 mV to with AF-CTLE. The power efficiency during burst write and read were 5.68 pJ/bit and 1.83 pJ/bit, respectively.