Fin-shaped Field-effect Transistors Research Articles

Physics-based modeling of surface potential and leakage current for vertical Ga2O3 FinFET

Gallium oxide (Ga2O3) is a promising ultra-wide bandgap material offering a large bandgap (>4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga2O3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga2O3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga2O3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga2O3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga2O3 power transistors.

4:2 Compressor Design for Low Leakage Applications in FinFET Technology

ABSTRACT The increased short-channel effects in the ultra-nanoscale regime limit the operation of complementary metal oxide semiconductor (CMOS) technology for future systems. To combat the issues in the ultra-nanoscale regime, fin-shaped field effect transistor (FinFET) technology is the best choice because of its numerous advantages over CMOS technology. FinFET enhances the further scaling of the devices and control over the channel. Therefore, this research paper presents the implementation of a low leakage 4:2 compressor in FinFET technology. A compressor is a general block, especially used in multiplier units and hence in digital signal processing (DSP) systems. The design of the low power compressor improves the overall efficiency of the DSP systems. An extensive study of the proposed low power 4:2 compressor at 7 nm technology node is done in the paper. Mentor Graphics tools are used for the circuit simulations and analyzes. The key parameters, such as leakage power, delay, power delay product (PDP), and the process voltage temperature (PVT) variations, are estimated for the performance evaluation. The proposed 4:2 compressor saves 87.33% of leakage power and is 75.90% more energy efficient compared to its conventional counterpart.

Study of the Reliability for the Leakage Mitigation Methods using FinFETs

Introduction: In the very large-scale integration (VLSI) industry, scaling plays an important role in providing compact size and high-speed digital circuits. The major drawbacks faced by logic circuits are power dissipation and process, voltage, and temperature (PVT) variations. In the VLSI industry, the prediction of variability tolerance capability is mandatory to know the future performance of the circuits. The impact of PVT variation is large in nanoscale logic circuits and it has the power to alter the output characteristics of any logic circuit. The reasons that cause PVT variations are manufacturing defects, environmental conditions, and mishandling issues. Aims and Objective: This paper aims to discuss the process variations and briefly describe the previous work related to variability and various factors involved in PVT simulations. It also provides the idea of Monte-Carlo simulation in the Cadence Virtuoso tool. Methods: In this paper, the impact of PVT variations on different fin-shaped field effect transistor (FinFET) circuits was evaluated using the Cadence Virtuoso tool. Monte-Carlo simulation was performed on various leakage reduction techniques for the domino logic with the help of a multi-gate predictive technology model (PTM) FinFET at a 16nm technology node. Results: The footer-less domino logic (FLDL) circuit is designed and simulated using different leakage reduction techniques for reliability analysis. Conclusion: Cascaded leakage control transistor (CLCT) approach shows 81.75%, 67.83%, and 51.25% less statistical mean value for power dissipation as compared to conventional, on-off logic (ONOFIC), and alternative ONOFIC approaches in the case of FLDL OR2 logic circuit, respectively.

FinFET based SRAM cells design in various topologies using different power reduction techniques

<p>In Very Large Scale Integration (VLSI) design, device scaling is restricted due to subthreshold swing limitations and short channel effects. This article discusses the role of different power reduction techniques in the implementation of 14 nm fin-shaped field-effect transistor (FinFET) centered static random access memory (SRAM) cells with good subthreshold swing and reduced short channel effects (SCE). Dynamic threshold and power gating are incorporated in SRAM cells to advance the memory cell performance by reducing static power dissipation in standby mode. The power analysis was performed on different SRAM cells with different transistor count i.e., 6, 7, 8, and 9. The performance of SRAM cell is analysed in power dissipation and is reduced by 20% using power gating method and in dynamic threshold it is reduced to nano watts due to less leakage power.</p>

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Background:The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.Objective:FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.Methods:An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).Results:The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased hybrid full adder using FinFETs shows the least energy consumption per switching. Fin- FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.Conclusion:MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale regime.

A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications

ABSTRACT Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (I ON /I OFF ) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at V DD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in I ON /I OFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches.

A Dual Core Source/Drain GAA FinFET

The emergence of fin-shaped field effect transistors (FinFETs) was governed by the requirement of the VLSI industry to include more functionalities per unit chip area. Enhanced gate control in a FinFET due to a surrounding gate architecture built on the fundamental geometry of a MOSFET made them highly compatible to the existing CMOS circuit applications. The announcement of a vertically stacked multiple FinFET structure named as Ribbon-FET by Intel Corporation in 2021 motivates the work presented in this article. This article proposes a dual core sourcedrain gate-all-around FinFET, and evaluates its performance in terms of variation in core doping concentrations through technology computer aided design (TCAD) simulations. The advantage of having a dual core in source and drain regions is the opportunity to tune the performance metrics of the device by altering the doping concentration in the outer, and inner cores. The response of the optimized architecture to presence of acceptor-like, and donor-like traps in oxide/ channel interface is presented. The acceptor-like traps affect the characteristics in its on-state, whereas the donor-like traps influence the off-state of the device. DIBL reduces with the introduction of interface traps.

Skeleton-Enhanced Discontinuous Galerkin Method for 3-D Nonlinear Semiconductor Modeling

We present a mesh skeleton-enhanced discontinuous Galerkin (DG) method, i.e., hybridizable DG, to solve the 3-D highly nonlinear semiconductor drift-diffusion model. This skeleton-enhanced DG algorithm is a remedy but a significant extension of the classical DG method, where only the degrees of freedom on the skeleton are involved as a globally coupled problem, thus reducing the global dimension from 3-D to 2-D and 2-D to 1-D. Furthermore, high-order nodal basis functions over tetrahedra are easily obtained, and meticulous mesh designs are circumvented for complex semiconductor modeling. Rigorous analytical solutions demonstrate that the convergence rate achieves an optimal order of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\emph{p}+1$</tex-math> </inline-formula> in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\bm{L}^{\bm{2}}$</tex-math> </inline-formula> -norm. Then, we also apply our algorithm to solve semiconductor devices, including a bipolar transistor and a trigate fin-shaped field-effect transistor. Compared with the conventional finite volume and finite element solvers, the proposed algorithm exhibits superior stability, convergence, and efficiency.

Leaky FinFET for Reservoir Computing with Temporal Signal Processing.

Reservoir computing can greatly reduce the hardware and training costs of recurrent neural networks with temporal data processing. To implement reservoir computing in a hardware form, physical reservoirs transforming sequential inputs into a high-dimensional feature space are necessary. In this work, a physical reservoir with a leaky fin-shaped field-effect transistor (L-FinFET) is demonstrated by the positive use of a short-term memory property arising from the absence of an energy barrier to suppress the tunneling current. Nevertheless, the L-FinFET reservoir does not lose its multiple memory states. The L-FinFET reservoir consumes very low power when encoding temporal inputs because the gate serves as an enabler of the write operation, even in the off-state, due to its physical insulation from the channel. In addition, the small footprint area arising from the scalability of the FinFET due to its multiple-gate structure is advantageous for reducing the chip size. After the experimental proof of 4-bit reservoir operations with 16 states for temporal signal processing, handwritten digits in the Modified National Institute of Standards and Technology dataset are classified by reservoir computing.

Reliability Analysis of FinFET Based High Performance Circuits

In the VLSI industry, the ability to anticipate variability tolerance is essential to understanding the circuits’ potential future performance. The cadence virtuoso tool is used in this study to assess how PVT fluctuations affect various fin-shaped field effect transistor (FinFET) circuits. In this research, high-performance FinFET-based circuits at 7 nm are discussed with a variation in temperature and voltage. The idea behind the technology is the improvement of power dissipation and delay reduction at the rise of temperature and reduced supply voltage. With the use of a multi-gate predictive model, simulation is carried out employing diverse domino logic at the 7 nm technology node of FinFET files. The proposed set-reset logic circuit and high-speed cascade circuit method shows less power dissipation and delay compared to the existing current mirror footed domino, high-speed clocked delay, and modified high-speed clocked delay with a variation of temperature and supply voltage. For the proposed set-reset logic circuit and high speed cascade circuit, a Monte Carlo simulation is done to find the mean and standard deviation. FinFET simulations are run on the suggested circuit for the reduction of delay for the rise of temperature and reduction of supply voltage from 0.7 V to 0.3 V. In comparison, the proposed method results in a maximum power decrease compared to existing ones. Compared to the existing one, proposed techniques achieve a maximum delay and area reduction.

Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET

The performance enhancement of integrated circuits relying on dimension scaling (i.e., following Moore’s Law) is more and more challenging owing to the physical limit of Si materials. Monolithic three-dimensional (M3D) integration has been considered as a powerful scheme to further boost up the system performance. Two-dimensional (2D) materials such as MoS2 are potential building blocks for constructing upper-tier transistors owing to their high mobility, atomic thickness, and back-end-of-line (BEOL) compatible processes. The concept to integrate 2D material-based devices with Si field-effect transistor (FET) is technologically important but the compatibility is yet to be experimentally demonstrated. Here, we successfully integrated an n-type monolayer MoS2 FET on a p-type Si fin-shaped FET with 20 nm fin width via an M3D integration technique to form a complementary inverter. The integration was enabled by deliberately adopting industrially matured techniques, such as chemical mechanical planarization and e-beam evaporation, to ensure its compatibility with the existing 3D integrated circuit process and the semiconductor industry in general. The 2D FET is fabricated using low-temperature sequential processes to avoid the degradation of lower-tier Si devices. The MoS2 n-FETs and Si p-FinFETs display symmetrical transfer characteristics and the resulting 3D complementary metal-oxide-semiconductor inverter show a voltage transfer characteristic with a maximum gain of ~38. This work clearly proves the integration compatibility of 2D materials with Si-based devices, encouraging the further development of monolithic 3D integrated circuits.

Robust Logic Circuits Design Using SOI Shorted-Gate FinFETs

The scaling of planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology has reached to its extremity. Double Gate (DG) device was introduced to derive the benefits of scaling gate lengths. Fin-shaped Field Effect Transistors (FinFETs) proved to be the best architecture to realize a double gate structure. In this paper, a static leakage control technique is proposed and a ring-oscillator of five inverters based on shorted gate (SG) FinFETs is simulated using the technique. The basic logic gates like Inverter, 2-input NAND gate, and 2-input NOR gate are simulated using the proposed technique. Leakage power and Power Delay Product (PDP) optimization of 93.46% and 97.78% has been found in 2-input SG FinFET-based proposed NAND gate compared to that of 2-input SG FinFET-based conventional NAND gate.Also, SG FinFET-based proposed 2-input NOR gate shows 98.03% and 98% optimization of leakage power and PDP,respectively compared to the SG FinFET-based conventional 2-input NOR gate. The proposed SG FinFET-based ring-oscillator shows a leakage power and PDP optimization of 62.12% and 35.56%, respectively in comparison to theconventional SG FinFET-based ring-oscillator. The reliability of the proposed circuit is calculated, which came out to be thehighest at 0.7V supply and 16nm process node for a 10% deviation in operating parameters. Also, the process parametervariation of leakage power, delay, and PDP of the proposed circuit came out to be proper and stable thus maintaining thefunctionality of the proposed circuit.

Polarity and Patterning Effect on Plasma Charging Levels by Metal-Gate Coupled Recorder Arrays

This work demonstrates a newly designed metal-gate coupled recorder for evaluating the plasma charging effect in fin-shaped field-effect transistor (FinFET) back-end-of-line (BEOL) processing steps. With more precise readings, the modified recorders are arranged in an array to further study the charging polarity and patterning effects during plasma processes. These recorder arrays can become a useful tool for process optimization for future CMOS technologies.

An efficient low power method for FinFET domino OR logic circuit

Advancement in the metal oxide semiconductor field effect transistor (MOSFET) technology leads to large power dissipation, and propagation delay due to extreme scaling of the transistor. So, very large-scale integration (VLSI) industry requires alternative options to meet the demands of the customers. Fin-shaped field effect transistor (FinFET) is new innovative device to replace the MOSFET technology in ultra-deep submicron (ultra-DSM) regime. FinFET mitigates power dissipation to the large extent as compared to the MOSFET, but still the impact of power dissipation degrades the circuit performance. Leakage reduction techniques are further needed in ultra-DSM regime to reduce the power dissipation. Domino logic is commonly used in large memories, and high-speed processors. In this article, a low power domino logic is proposed using FinFET devices. The proposed method is compared to the existing similar domino logic approaches for the different performance metrics at 7 nm technology node using Cadence's tools. The proposed method effectively reduces the leakage power dissipation, and delay penalty for the different logic circuits. The reliability of the domino OR logic is checked by estimating the temperature, and multiple parallel fins variations. The proposed method has a high noise tolerance capacity in term of unity noise gain (UNG) for the domino OR logic as compared to the existing approaches.

Performance Optimization of Carbon Nano-Tube Field Effect Transistors by Tuning Parameters

As transistors are scaled down to keep up with Moore's law, the semiconductor industry is facing several challenges due to the limitation of traditional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology. To overcome this issue of scalability, various other technologies are being researched. Among them are Carbon Nano-Tube Field Effect Transistors (CNTFET), Ribbon Field Effect Transistors (RibbonFET), Graphene Nanoribbon Field Effect Transistor (GNRFET), and Fin shaped Field Effect Transistor (FinFET), which can substitute MOSFETs. Due to carbon nanotubes' excellent conductivity supremacy, CNTFETs are a promising new solution. However, implementing a CNTFET and making circuits from it is still challenging as CNTFETs can exhibit properties of both semiconductor and metal depending on various parameters. This paper will illustrate the characteristics of the CNTFET, compare the power consumption and propagation delay of basic logic gates made using the CNTFET and MOSFET technology. The parameter tuning is done by measuring the power and delay for all parameter values. The Simulation of CNTFET is done on the Stanford CNTFET model using H-Spice.

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

This paper depicts the analog investigation of a Novel Stacked Oxide Top Bottom Gated Junctionless (TBG-JL) Fin-shaped Field Effect Transistor (FinFET) structure. The structure is designed in this way to enhance the switching performance and curtail the Short Channel Effects (SCEs). The study is done on Silvaco Atlas TCAD tools for the Novel Stacked Oxide FinFET device and analyzed against Top-Bottom Gated Junctionless FinFET and Traditional FinFET. The Novel device shows 280 times improvement in switching ratio when stacked against the Traditional JL FinFET at identical gate length at room temperature (300K). The results from device simulation affirm that the Novel device has better analog performance over Traditional Junctionless FinFET and diminishes the Short Channel Effects (SCEs) a cut above the Traditional Junctionless FinFET.

Design and simulation of a gas sensitive junctionless FinFET based on conducting polymer as the gate material

In this study, we demonstrate a multi-gas sensing device utilizing junctionless Fin-shaped Field Effect Transistor (FinFET) with conducting polymer as the gate material. The higher gas response is explained based on workfunction modulation of the conducting polymer gate, Poly(p-phenylene), upon gas molecule absorption. By definition, threshold voltage and off-state current variation before and after gas absorption are considered as two different measures for assessing the responsivity and sensitivity of the sensor. Basically, the main focus of this paper is designing a low power device, in which the change in the electrical characteristics of the device under gas exposure can be detected even in the absence of the gate bias. The high sensitivity of the proposed FinFET device as a gas sensor is mainly attributed to the large surface area of the 3D structure. We optimize the gas-sensing properties by investigating impact of critical physical and structural design parameters on the responsivity and selectivity of the sensor. In addition, statistical analysis is carried out to calculate coefficient of variation (CV) measure, for assessing the change in the responsivity of the gas sensor based on variation of main design parameters. Our results provide a route to design a low power CMOS compatible gas sensor that has fast response with high distinguishing selectivity and can be scaled down to nanoscale regime.

Study on memory characteristics of fin-shaped feedback field effect transistor

The nonvolatile and volatile memory characteristics of feedback field-effect transistors (FBFETs) with nitride charge storage layers were theoretically studied. Because of the electrons and holes stored in the nitride layer, the threshold voltage (V TH) window of 0.6 V was opened/observed. And, with the help of the formation of a positive feedback loop in the p+–n+–p–n+ doped silicon region in FBFET, it turned out that the read delay time of the FBFET for nonvolatile memory applications can be shorter than 1 ns. On the other hand, for the volatile memory applications, the FBFET can implement (a) non-destructive read operations owing to the self-sustaining feedback loop characteristic, and (b) a significantly long retention time which can suppress the power dissipation in refresh. Furthermore, the operation scheme of volatile memory mode can be simplified by setting gate voltage conditions for the hold and read operations to be identical to each other. The FBFET showed its on-state drive current of 6 × 10−5 A μm−1 and the on-/off-current ratio of 109. The potential of merging nonvolatile and volatile memory devices in a single cell is discussed and demonstrated in this work.

Performance Comparison for FinFET Nanoscale Static and Domino Logic Circuits

The future prospects of complementary metal oxide semiconductor (CMOS) technology are estimated to be replaced by fin-shaped field effect transistor (FinFET) owing to its strong channel control, high driving capability and ease of fabrication. This paper envisages the effects of voltage, temperature and fin variation on power dissipation and delay for static and domino logic circuits. Circuit behavior becomes unpredictable due to process, voltage and temperature (PVT) variations such as irregular power consumption and performance deviation. It also accelerates circuit deterioration and makes them ineffective. The important circuit level leakage power reduction techniques like LCNT, LECTOR and INDEP have been applied to basic gates, 3-bit carry look ahead adder (CLA) and domino logic circuits at 16 nm FinFET technology. It is found that power delay product (PDP) in CLA using INDEP technique exhibits 61.48% less than conventional CLA. Leakage power reduction techniques have also been verified for the footer domino logic (FDL) circuit and performed Monte Carlo simulations for 10000 samples for reliability analysis. INDEP circuits are robust to PVT variations. The simulations have been completed using Cadence Virtuoso tool.

Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

We analyzed the performance, power, area of 3 nm node fin and nanosheet (NS) field-effect transistors (FETs) implementing buried power rail (BPR) after full calibration to 5 nm node hardware. Fin-shaped FETs (FinFETs) have smaller <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> delay than do NS FETs (NSFETs) under the same footprint and two-fin configuration. Larger number of NS channels boost drive currents but also increase gate capacitances as a tradeoff. Compared with 7 and 3 nm standard cells achieve 75% cell area scaling in average. Cells using BPR decrease delay, transition time, internal power, and pin capacitances under the same area. Larger cells such as D-flip flop (DFF) and XOR decrease those further because the parasitic capacitances of metal layers between signal and power/ground decrease much. NS-based cells using BPR can improve delay and transition time by increasing the number of NS channels, but increase internal power and pin capacitance. Overall, fin-based cells using BPR have smaller energy delay product by 12% compared with those without BPR and by 10% compared with NS-based cells using BPR.