Fin Field Effect Transistor Research Articles

Prediction of Electrical Characteristics of Fin Field-effect Transistor Devices Based on Simulation Using Deep Learning Method

Prediction of Electrical Characteristics of Fin Field-effect Transistor Devices Based on Simulation Using Deep Learning Method

Developments and Applications of Field-Effect Transistor

This review article delves into the development and future prospects of Field-Effect Transistors (FETs), tracing their evolution from the nascent theoretical concept proposed by Julius Lilienfeld in 1925. Over the years, FETs have traversed significant milestones, marking their progression from fundamental ideas to practical applications. Key among these milestones are the advent of the Metal-Oxide-Semiconductor FET (MOSFET), which revolutionized the electronics industry, the Fin FET, offering enhanced performance through three-dimensional structures, and the GateAll-Around FET (GAA-FET), promising even greater control and efficiency. It provides a systematic comparison of these technologies, dissecting their structural differences, evaluating performance metrics such as speed, power consumption, and scalability, and exploring their potential applications across diverse domains. While recent advancements in FET technology have primarily focused on structural innovations to mitigate the short channel effect, researchers are also actively exploring alternative avenues, including the use of novel materials and refined fabrication techniques, to further enhance FET performance and unlock new possibilities for electronic devices. This multifaceted approach underscores the dynamic and ever-evolving nature of FET technology, positioning it as a cornerstone for future advancements in electronics.

Performance Analysis of JL-FinFET with Varied Non-Uniform Doping Concentrations, Fin Height and Fin Width using Device Simulator

With the growth of the MOSFET technology, the size of the transistor becomes smaller which can lead to Short-Channel Effects (SCEs). In order to address the SCEs, multi-gate transistor such as Fin Field-Effect Transistor (FinFET) has been invented. Meanwhile, it is found that the conventional transistor with junctions also has its drawbacks and limitations due to the decrease in the gate length. The SCEs can occur and affect the overall performance of the device with lower switching times and lower current density . In order to address these limitations, new structure of transistor without junction known as a junctionless (JL) transistor has been proposed. In this work, the impact of uniform versus non-uniform doping concentrations, fin height (Hfin) and fin width (Wfin) in JL-FinFET were investigated by using Technology Computer Aided Design (TCAD) Tools. It was found that non-uniform doping concentration of 4 x1018 cm-3 for the source/drain and of 4 x1017 cm-3 for the channel, together with Hfin of 20 nm and Wfin of 4 nm provide the best electrical performance of Ioff = 6.45 x10-17 A, Ion = 6.14 x10-6 A, Ion/Ioff = 9.52 x1010 and DIBL = 11 mV/V. The outcome of this research work can be used as a basis to understand JL-FinFET biosensors for medical applications and more complex JL structures.

Temperature dependence of the low-frequency noise in AlGaN/GaN fin field effect transistors

Low-frequency (LF) noise measurements are compared for Schottky-gate AlGaN/GaN heterostructure planar and fin field-effect transistors (FinFETs) as functions of gate voltage and measuring temperature. The noise of each device type is consistent with a carrier number fluctuation model. Similar effective defect-energy Eo distributions are derived for each of the two device architectures from measurements of excess drain-voltage noise-power spectral density vs temperature from 80 to 380 K. Defect- and/or impurity-related peaks are observed in the inferred energy distributions for Eo < 0.2 eV, Eo ≈ 0.45 eV, and Eo > 0.6 eV. Significant contributions to the LF noise are inferred for nitrogen vacancies and ON and FeGa impurity complexes. Ga dangling bonds at fin interfaces with gate metal are likely candidates for enhanced noise observed in FinFETs, relative to planar devices. Reducing the concentrations of these defects and impurity complexes should reduce the LF noise and enhance the performance, reliability, and radiation tolerance of GaN-based high electron mobility transistors.

A Two-Step Dry Etching Model for Non-Uniform Etching Profile in Gate-All-Around Field-Effect Transistor Manufacturing.

The Gate-All-Around Field-Effect Transistor (GAAFET) is proposed as a successor to Fin Field-Effect Transistor (FinFET) technology to increase channel length and improve the device performance. The GAAFET features a complex multilayer structure, which complicates the manufacturing process. One of the most critical steps in GAAFET fabrication is the selective lateral etching of the SiGe layers, essential for forming the inner-spacer. Industry commonly encounters a non-uniform etching profile during this step. In this paper, a continuous two-step dry etching model is proposed to investigate the mechanism behind the formation of the non-uniform profiles. The model consists of four modules: anisotropic etching simulation, Ge atom diffusion simulation, Si/SiGe etch selectivity calculation and SiGe selective etching simulation. By calibrating and verifying this model with experimental data, the edge rounding and gradient etching rates along the sidewall surface are successfully simulated. Based on further examination of the influence of chamber pressure on the profile using this model, the inner-spacer shape is improved experimentally by appropriately reducing the chamber pressure. This work aims to provide valuable insights for etching process recipes in advanced GAAFETs manufacturing.

Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance

This work presents two innovative 12T cells combining tunnel field-effect transistor (TFET) and fin field-effect transistor (FinFET) technologies. These cells address reverse bias current issues by incorporating separate paths for reading data and write enhancement cut transistors, enhancing hold/read/write static noise margin (H/R/WSNM), reducing read time, and minimizing power consumption from TFET leakage. At 0.6 V, the first (second) SRAM cell shows a WSNM improvement over O_7T, 8T, CA_10T, 12T, and HF_10T cells by 152 % (93 %), 152 % (93 %), 157.7 % (97.5 %), 95 % (50 %), and 104 % (57 %), respectively. The leakage power of the first (second) 12T TFET SRAM cell is two (four) orders of magnitude lower than O_7T and 8T SRAM cells. These hybrid SRAM cells also exhibit faster read operations across VDD voltage levels (0.3 V–1 V) and the first 12T cell demonstrates shorter write access times than 12T and CA_10T SRAM cells. These characteristics make the proposed cells particularly suitable for energy-efficient IoT devices and medical applications, where balancing power, area, performance, and data integrity is critical.

Analysis of voltage mode quadrature oscillator based on fin field-effect transistor

This study introduces a new voltage mode sinusoidal quadrature oscillator (V-M.S.Q.O.) that employs multioutput Z copy voltage differencing transconductance amplifiers (M-Zc-VDTA) as an active filter based on FinFET transistor. The suggested circuits have low passive and active sensitivities, and they may be constructed as integrated circuits using only two M-Zc-VDTAs and three grounded capacitors. The circuits produce two (VM) sinusoidal quadrature oscillator voltage results by adjusting the electronic base current and frequency of the oscillation condition separately. FinFET technology lowers power consumption while improving circuit performance. They can also produce amplitude shift keying-amplitude modulation signals for communication electronics systems and provide electrical basis control of output current amplitude. Using the Cadence Virtuoso tool with a 7 nm parameter, simulation results were obtained for the suggested circuits.

Improved Subthreshold Characteristics of Epi-Silicon FinFET via Fin Surface Passivation Technologies

As demand for advanced integrated circuits (ICs) continues to grow, fin field-effect transistors (FinFETs) have remained highly influential in the IC market because of their mature fabrication process and powerful driving capabilities. However, the ion bombardment that occurs during the reactive ion etching (RIE) process used to form the fin structure increases the fin’s surface roughness and results in a high interfacial state density (D it ), which hinders further improvement in the subthreshold swing (SS) of FinFETs. To overcome this issue, this study proposes two oxidative trimming methods for use on the fin structures to improve their interface quality. It is found that conventional thermal oxidation and low-temperature oxidation processes reduced the channel D it by 73.31% vs 71.17%, respectively. Furthermore, the corresponding SS values of the device improved to 72.76 and 71.72 mV dec−1, respectively. The technical solutions proposed in this paper represent a promising approach for performance optimization of FinFETs and other advanced devices.

Ga2O3 fin field-effect transistors with on-axis (100)-plane gate sidewalls fabricated on Ga2O3 (010) substrates

Ga2O3 fin field-effect transistors (FinFETs) were fabricated on β-Ga2O3 (010) substrates, which had on-axis (100)-plane gate sidewalls treated by nitrogen radical irradiation. The typical FinFET with a fin width (W fin) of 400 nm demonstrated decent on-state device characteristics such as a low specific on-resistance of 6.9 mΩcm2, a high drain current on/off ratio of over 109, and a subthreshold slope of 82 mV/decade. The threshold voltage (V th) of the FinFETs increased with decreasing W fin, and enhancement-mode operation with V th > 0 V was achieved for W fin < 800 nm.

Junctionless accumulation-mode SOI ferroelectric FinFET for synaptic weights

In this work, a novel silicon-on-insulator (SOI) based junctionless-accumulation-mode (JAM) ferroelectric (FE) fin field effect transistor (FinFET) is proposed along with its fabrication process flow at a 3-nm node for synaptic weights. The proposed JAM FE FinFET device can be easily integrated with the fabrication flow of p-FinFET in SOI process flow. The proposed device can be easily incorporated into standard FinFET SOI technology and thus is very attractive with respect to previously proposed devices. Further, using a well-calibrated 3D TCAD simulation setup, we show that the device effectively replicates the behavior required for neuromorphic computing applications. The outcomes of the proposed study emphasize the significance of using the JAM FE FinFET as a synaptic weight device that exhibits a 76 % higher nonvolatile conductance range in the ON-state over existing junctionless and conventional FE FinFET devices. Our simulations show that the proposed device offers continuous linear conductance variation and symmetric switching characteristics, which are essential for neuromorphic applications.

An embedded gate gate-all-around FinFET for biosensing application

A dielectric modulated embedded gate gate-all-around fin field-effect transistor (EGGAA-FinFET) has been proposed for label-free detection applications of biomolecules in this article. The design expands the biomolecule capture area by establishing a cavity below the embedded gate. The performance of EGGAA-FinFET and FinFET biosensors is analyzed in a comprehensive comparison in terms of electrical performance, sensitivity and selectivity. Some important biosensing characteristics for EGGAA-FinFET (FinFET) have been calculated to be 0.43 V (0.32 V) for threshold voltage sensitivity, 2.22 × 106 (8.32 × 104) for current switching ratio sensitivity, and 0.75 (0.65) for subthreshold swing sensitivity. To determine the optimal structure of the biosensor, the effect of structural parameters on sensitivity is investigated. In addition, the effect of the filling factor on the biosensor is considered. The real-world performance of biosensors is assessed using the linearity parameter, showing that the EGGAA-FinFET biosensor has better noise resistance compared to the FinFET biosensor.

Study on the regulation factors and mechanism of self-heating effects in non-rectangular 14 nm bulk FinFET*

Abstract This work investigates the innovative design of a 14 nm bulk 3D non-rectangular structure fin field-effect transistor (FinFET). By incorporating a cylindrical trapezoidal structure into the upper portion of the FinFET, it transcend the limitations posed by the self-heating (SH) effect observed in traditional rectangular fins.Through the density gradient model and thermal conduction model, the changes in the electron carrier temperature and lattice temperature of the channel are studied, and the relationship between electrical properties and thermal resistance was further analyzed, revealing the effect of SH on the threshold voltage and switching speed of the device. In addition, the SH effect of the doping of source and drain extension regions was also explored, and the effects of electron mobility changes at different ambient temperatures were also studied to clarify their impact on the electrical properties. Ultimately, this work offers novel insights into the design, optimization, and reliability studies of device structures affected by SH effects.

Study of Inner Spacer Module Process for Gate All Around Field Effect Transsistors

Gate-All-Around(GAA) transistor is the most competitive device for the replacement of Fin Field-Effect Transistor (FinFET). Integrating the inner spacer module into process flow of manufacturing GAA devices still faces significant challenges.In this study, dummy gates were included and the most critical processes for inner spacer, such as cavity etching, dielectric material conformal filling and precise etching back process were studied.The inner spacer cavity with a depth of 10.10 nm was achieved using isotropic etching, and dielectric filling was completed by low pressure chemical deposition (LPCVD). Finally, an inner spacer with 9.35 nm thickness is formed after precise etching the dielectric material. Furthermore,to verify the physical isolation of the inner spacer, a selective epitaxy was developed on the Source/Drain region, achieving better process results. This research will provide important references for the industry to manufacture GAA devices, especially inner spacers.

Influence of Doping Engineering in 1 μm Drift Layer Quasi‐Vertical Fin Field‐Effect Transistor for Achieving &gt;139 V Breakdown Voltage

A quasi‐vertical gallium nitride (GaN) fin field effect transistor (FinFET) is designed and analyzed to assess the performance of electrical parameters. The device is deployed on a silicon carbide (SiC) substrate and analyzed using technology computer‐aided design (TCAD). The donor concentration in the critical regions is identified as a significant limiting factor for FinFET electrical properties. Hence, the influence of channel and drift layer doping concentrations (Nd) on performance characteristics is investigated in this work. The electrical characteristics such as threshold voltage, ION/IOFF ratio, subthreshold swing (SS), specific ON‐resistance, and breakdown voltage (VBV) are evaluated for various doping profiles. The doping profile with channel and drift layer concentration of 4 × 1015 cm−3 for a 300 nm fin width and 1 μm thick drift layer exhibits normally OFF behavior with a threshold voltage (Vt) of 1.5 V. It also demonstrates a VBV of 139 V. The corresponding doping profile reveals a low SS of 61 mV dec−1, which is comparable to other similar power devices. This demonstrates the significant potential of the device for medium‐power switching applications.

Valley-Free Silicon Fins Caused by Shear Strain.

Electron spins confined in silicon quantum dots are promising candidates for large-scale quantum computers. However, the degeneracy of the conduction band of bulk silicon introduces additional levels dangerously close to the window of computational energies, where the quantum information can leak. The energy of the valley states-typically 0.1meV-depends on hardly controllable atomistic disorder and still constitutes a fundamental limit to the scalability of these architectures. In this work, we introduce designs of complementary metal-oxide-semiconductor (CMOS)-compatible silicon fin field-effect transistors that enhance the energy gap to noncomputational states by more than one order of magnitude. Our devices comprise realistic silicon-germanium nanostructures with a large shear strain, where troublesome valley degrees of freedom are completely removed. The energy of noncomputational states is therefore not affected by unavoidable atomistic disorder and can further be tuned insitu by applied electric fields. Our design ideas are directly applicable to a variety of setups and will offer a blueprint toward silicon-based large-scale quantum processors.

Advantages, manufacturing processes and challenges of FinFET technology

Abstract As an emerging cutting-edge integrated circuit technology, Fin Field Effect Transistor (FinFET) has not only successfully broken through the limitations of the 22nm node since its development in 1998, but it still maintains considerable vitality and is developing into smaller sizes. As an improvement over traditional MOSFET technology, FinFET offers many technical advantages, which practically solve the challenges encountered by traditional MOSFET. The FinFET process technology is incompatible with planar MOSFET process technology. Moreover, since the development of Finfet technology, there have been many technical challenges. The first half of this article mainly introduces the differences and advantages between FinFET and traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and briefly outlines its manufacturing process. The second half explains the challenges and hopes on the development path of FinFET technology. I believe this article can provide a reference for integrated circuit designers when understanding FinFET technology, and provide guidance and reference for beginners.

Ultra-Efficient Low-Power Retinal Nano Electronic Circuit for Edge Enhancement and Detection Using 7 nm FinFET Technology

Ultra-Efficient Low-Power Retinal Nano Electronic Circuit for Edge Enhancement and Detection Using 7 nm FinFET Technology

Prediction of electrical properties of GAAFET based on integrated learning model

As device feature sizes continue to decrease and fin field effect transistors reach their physical limits, gate all around field effect transistors (GAAFETs) have emerged with larger gate control areas and stackable characteristics for better suppression of second-order effects such as short-channel effects due to their gate encircling characteristics. Traditional methods for studying the electrical characteristics of devices are mostly based on the technology computer-aided design. Still, it is not conducive to developing new devices due to its time-consuming and inefficient drawbacks. Deep learning (DL) and machine learning (ML) have been well-used in recent years in many fields. In this paper, we propose an integrated learning model that integrates the advantages of DL and ML to solve many problems in traditional methods. This integrated learning model predicts the direct current characteristics, capacitance characteristics, and electrical parameters of GAAFET better than those predicted by DL or ML methods alone, with a linear regression factor (R 2) greater than 0.99 and very small root mean square error. The proposed integrated learning model achieves fast and accurate prediction of GAAFET electrical characteristics, which provides a new idea for device and circuit simulation and characteristics prediction in microelectronics.

Anisotropic exchange interaction of two hole-spin qubits

Semiconductor spin qubits offer the potential to employ industrial transistor technology to produce large-scale quantum computers. Silicon hole spin qubits benefit from fast all-electrical qubit control and sweet spots to counteract charge and nuclear spin noise. However, the demonstration of a two-qubit interaction has remained an open challenge. One missing factor is an understanding of the exchange coupling in the presence of a strong spin–orbit interaction. Here we study two hole-spin qubits in a silicon fin field-effect transistor, the workhorse device of today’s semiconductor industry. We demonstrate electrical tunability of the exchange splitting from above 500 MHz to close-to-off and perform a conditional spin-flip in 24 ns. The exchange is anisotropic because of the spin–orbit interaction. Upon tunnelling from one quantum dot to the other, the spin is rotated by almost 180 degrees. The exchange Hamiltonian no longer has the Heisenberg form and can be engineered such that it enables two-qubit controlled rotation gates without a trade-off between speed and fidelity. This ideal behaviour applies over a wide range of magnetic field orientations, rendering the concept robust with respect to variations from qubit to qubit, indicating that it is a suitable approach for realizing a large-scale quantum computer.

Advancements And Applications of Finfet Technology in Modern Semiconductor Engineering

This comprehensive study presents an in-depth analysis of Fin Field-Effect Transistor (FinFET) technology, a significant innovation in semiconductor technology, focusing on its structural attributes, applications, and future prospects. FinFETs, characterized by their distinctive fin-like channels, are pivotal in overcoming the limitations of traditional MOSFETs, particularly in the context of device miniaturization. The paper begins by exploring the basic theory and structural characteristics of FinFETs, emphasizing their enhanced control over short channel effects and reduced leakage currents in scaled-down devices. Attention is then directed towards the integration of FinFET technology in Static Random-Access Memory (SRAM), detailing how FinFETs contribute to improved stability and efficiency in memory storage. Another crucial application discussed is in the biomedical field, where FinFETs have facilitated the development of advanced instrumentation amplifiers and sensitive sensors, marking a leap in medical electronics. The paper concludes by addressing the challenges encountered by FinFETs as fabrication approaches the 5-7nm scale, including their physical and structural limitations. It also highlights ongoing research in structural modifications and material innovations like Gate-All-Around FETs and alternative materials, underscoring the continued evolution and relevance of FinFET technology in the ever-advancing semiconductor industry.