Fin Field Effect Transistor Research Articles

A new physical insight into the zero-temperature coefficient with self-heating in silicon-on-insulator fin field-effect transistors

The conflicting impacts of temperature on the threshold voltage and mobility, and consequently on the transfer characteristics of a MOSFET, result in a zero-temperature coefficient (ZTC) point. This point is very important for ensuring the stability of the circuit against temperature variations, as the drain current is temperature independent at this bias voltage. In this work, for the first time, we analyze ZTC bias-point instability caused by the self-heating effect (SHE). For this, we discuss the impact of lattice and carrier temperatures, influenced by the SHE, on the ZTC point, which is important in fin field-effect transistors. We report that the SHE causes the ZTC gate bias voltage to be lowered significantly, by about 16% of the overdrive voltage. We also explain the physics of this phenomenon and present a model to explain this change in the ZTC bias caused by the SHE. We discuss the relation between the change in ZTC due to changes in the threshold voltage, saturation velocity, and their temperature derivatives. Our results also show that the drift of the ZTC (i.e. ) is more critical at higher drain-to-source voltages (V DS). It is important, from an analog-circuit point of view, to predict the ZTC bias point drift caused by the SHE. Furthermore, a common-source amplifier biased at the ZTC predicted by our model-based method is simulated to validate the stability of the circuit against temperature variations. To improve the device design, the device dimensions are optimized to minimize the drift of the ZTC.

CMOS Loves 5G [Book/Software Reviews

This book looks at ways in which CMOS is pushing the frequency boundary. After an introductory chapter, the book splits into three parts: eight chapters on systems, four chapters on components, and a final chapter on fin field-effect transistors (FinFETs) and process technology. It is a fascinating tour of applications, critical components, and technology. The book has 14 chapters and almost 30 different authors, representing a mix of universities, research centers, and businesses. Each chapter has a different lead author, which makes for a wide variety of perspectives. Almost all of the chapters have background, measurements, and design examples, which create a very practical work. With all that said, this book is not exactly coherent, as there is much overlap and some duplication. All in all, however, this is an excellent overview and starting point for further study and work. I am sure you will enjoy it. This book begins with a nice summary of 5G evolution from previous systems and a view toward automotive radars. This book is an excellent and timely reference for anyone getting into this area or actively

Voltage gain improvement of the operational transconductance amplifier designed with silicon-on-insulator fin field effect transistor after being exposed to proton-irradiation

In this work, the influence of proton-irradiation in the voltage gain of two-stage operational transconductance amplifier (OTA) designed with silicon-on-insulator (SOI) fin field effect transistors (FinFETs) is studied. The OTA simulations were performed using Verilog-A approach based on experimental data extracted from the SOI FinFET electrical characterization, before and after proton-irradiation. The OTA is designed with SOI FinFETs of fin widths (W fin) of 20 nm, 120 nm, and 870 nm, all in the same predefined inversion region (g m/I D = 8 V−1). All evaluated OTA circuits exposed to proton-irradiation presented a voltage gain increase (compared with pre-irradiation circuits), of 0.87 dB, 1.19 dB, and 6.16 dB for fin widths of 20 nm, 120 nm, and 870 nm, respectively. The results show that despite the typical radiation effect of degradation of the individual transistors (it being more severe for larger fin width SOI FinFET), these effects combined in OTA circuits result in an unexpected improvement in DC voltage gain, especially for wider fins. Focusing on the fin width impact on the OTA voltage gain, before and after proton-irradiation, it is much greater for narrow fin width SOI FinFET thanks to the better Early voltage.

Quantitative evaluation of process-induced line-edge roughness in FinFET: Bayesian regression model

With the aggressive scaling down of the minimum feature size of advanced metal–oxide–semiconductor devices, it has become imperative to design and fabricate process-variation-immune devices. Technology computer-aided design simulations are typically used to test thousands of devices for process-variation immunity, but the process is computationally expensive. In this work, we propose a novel approach to simulate and predict the current–voltage characteristics of fin field-effect transistor devices with process-induced line-edge roughness (LER), within a few seconds. We exploit the Bayesian linear regression model to estimate the mean and standard deviation of the drain-to-source current (I DS) for an arbitrary gate voltage (V GS) and LER profile. We evaluate the prediction accuracy in terms of the mean absolute percentage error (MAPE) and root mean square error (RMSE). The MAPEs for the mean and standard deviation of I DS are <1% and <20%, respectively, and the corresponding RMSEs are 0.0804 and 0.0263, respectively. Once the I DS–V GS distribution is estimated by means of this novel approach, the distributions of other device metrics such as the threshold voltage and off-state leakage current can be estimated.

Leakage reduction technique for nano-scaled devices

PurposeThe purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.Design/methodology/approachBecause of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.FindingsThis study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.Originality/valueAll the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

High-k metal gate technology improves the performance and reduces the gate leakage current of metaloxidesemiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|Vt|) but also converted n- to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n- and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift ( ${\Delta }$ V $_{T}$ ), pre-existing traps ( ${\Delta } {N} _{\mathrm {HT}}$ ), generated traps, and their relative contributions were studied. The time exponents of ${\Delta }$ V $_{T}$ , the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B2H6-based W-filling metal, a 34% reduction in the fresh interface states, reduced ${\Delta }$ V $_{T}$ , and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of ${\Delta } {N} _{\mathrm {HT}}$ is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.

Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

Cyclic approach for silicon nitride spacer etching in fin field-effect transistors and stacked nanowire devices

Spacer etching in 3D CMOS technologies has become a very challenging step to be able to complete the etching while preserving channel and shallow trench insulation materials. The formation of parasitic spacers along fin sidewalls requires a lengthy overetch compared to conventional planar integrations to remove these undesired features, thereby drastically increasing the needed etching selectivities between silicon nitride, silicon (or SiGe), and silicon oxide. Based on an alternative etching chemistry, a new approach is assessed in this work, whose principle relies on selective passivation with an oxidelike material replacing the fluorine-containing organic layer encountered in dielectric etching with common fluorocarbons. Surface composition analyses demonstrate the preferential deposition on silicon with respect to silicon nitride yielding a high selectivity measured through etch rate tests on blanket films. The selectivity achieved is compatible with 3D CMOS spacer etching requirements. Despite the benefits shown by this alternative chemistry, some limitations prevent reaching the thorough elimination of parasitic spacer. A cyclic approach alternating selective passivation and nonselective etching is developed to overcome these limitations, which still provides effective silicon protection from etching. This cyclic sequence is evaluated on nanowire-type patterned structures and shows the complete removal of the parasitic spacer while providing a silicon loss of less than 2 nm. Work in development currently carries on to further improve this process and to fulfill all specifications for 3D CMOS spacer etching.

Machine learning-based modeling and operation of plasma-enhanced atomic layer deposition of hafnium oxide thin films

Plasma-enhanced atomic layer deposition (PEALD) has demonstrated its superiority at coating ultra-conformal high dielectric thin-films, which are essential to the fin field-effect transistors (FinFETs) as well as the advanced 3D V-NAND (vertical Not-AND) flash memory cells. Despite the growing research interest, the exploration of the optimal operation policies for PEALD remains a complicated and expensive task. Our previous work has constructed a comprehensive 3D multiscale computational fluid dynamics (CFD) model for the PEALD process and demonstrated its potential to enhance the understanding of the process. Nevertheless, the limitation of computational resources and the relatively long computation time restrict the efficient exploration of the operating space and the optimal operating strategy. Thus, in this work, we apply a 2D axisymmetric reduction of the previous 3D model of PEALD reactors with and without the showerhead design. Furthermore, a data-driven model is derived based on a recurrent neural network (RNN) for process characterization. The developed integrated data-driven model is demonstrated to accurately characterize the key aspects of the deposition process as well as the gas-phase transport profile while maintaining computational efficiency. The derived data-driven model is further validated with the results from a full 3D multiscale CFD model to evaluate model discrepancy. Using the data-driven model, an operational strategy database is generated, from which the optimal operating conditions can be determined for the deposition of Hafnium Oxide (HfO2) thin-film based on an elementary cost analysis.

Nanoscale Transistor Variability Modeling: How Simple Physics Enables a Powerful Prediction Platform

Process-induced variation (PIV) is the major bottleneck for using advanced CMOS technology efficiently. Even though the multigate nature of the fin field effect transistor (FinFET), nano-wire FET (NWFET), and nanosheet FET (NSFET) make the device robust toward the short channel effects (SCEs), unpredictable device-to-device variation caused by unwanted PIV remains a challenge for the designers. In this article, we propose a generic variability model to describe the impact of PIV on performance parameters of advanced devices. The major focus of this article is to demonstrate two independent analytical models capturing the impact of metal gate granularity (MGG) and line edge roughness (LER) on the threshold voltage ( V T ) of FinFET. The proposed model is not only limited to the variability estimation of V T , but also capable of estimating the on-current ( I on), subthreshold slope (SS), and off-current ( I off) distribution due to LER accurately. Both the models are generic enough to be extended to be used for NWFET, and NSFET, and utilizes simple physics and mathematics, therefore, it can be implemented in any platform. The models are 100-1,000 times faster in comparison to the technology CAD (TCAD) simulations, and accuracy is on par with the TCAD results. Such models, when integrated with the existing nominal SPICE setup, the circuit-level performance prediction will be comparable to the experimental results. As the models take process-generated variations as an input to produce corresponding performance variation, it will further enable the co-optimization of the process as well as the circuit performance.

Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET

In this study, an analytical model for surface potential and threshold voltage for undoped (or lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated using transistor computer aided design (TCAD) simulation. The threshold voltage with channel length 50 nm was compared with the published experimental results achieved from tri-gate FinFET. Separate solutions of 2D Poisson’s equation were obtained for both symmetric and asymmetric double gate FinFET and combined using the perimeter-weighted sum approach to achieve the surface potential for TG-FinFET. The inversion charge model was used to find the threshold voltage of the above mentioned device. The results of the model were obtained for different channel lengths, fin widths and fin heights on the silicon substrate. A comparative study of hafnium dioxide (HfO2) and silicon dioxide (SiO2) for the same oxide thickness was delineated to depict the influence of the high dielectric material on the model of FinFET. As anticipated, the oxide thickness of HfO2 is greater than SiO2 to maintain the same surface potential. The result of the analytical model was well agreed with the TCAD simulation outcome. Hence, it can be considered as a promising model in device technology.

Random polarization distribution of multi-domain model for polycrystalline ferroelectric HfZrO2

Device dimension scaling down to be comparable to the domain size of polycrystalline ferroelectric HfZrO2 (HZO) is evaluated for subthreshold swing (SS) and drain-induced barrier lowering (DIBL) by numerical simulation. The proposed multi-domain modeling involves polarization random location in HZO and probability with Gaussian distribution, as well as being integrated with the Landau–Khalatnikov equation. A small device with a few domains exhibits steep SS compared with large dimension with many domains. The N-DIBL (negative-DIBL) is also estimated by using this model, and the negative capacitance effect retards the short-channel effects significantly. The trend of the experimental data and simulation results of fin field-effect transistors and planar field-effect transistors is consistent with nano-scale and micro-scale devices, respectively.

Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node

A flexible framework is obtained for enhancing both the thermal and electrical performance of fin field-effect transistor (FinFET) technology. Investigation of the nanoscale heat conduction within a short-channel field-effect transistor can be regarded as an emerging challenge related to future-generation transistors. In this work, we report the electrothermal transport in a 10 nm silicon-on-insulator (SOI) FinFET based on the dual-phase-lag model and modified drift-diffusion motions. We found that electron mobility decreases along the channel due to carrier confinement under higher electric field. In addition, the surface detection temperature indicates that the self-heating process is localized between the source and drain region. As promising results, high-κ metal-oxide and lower thermal boundary resistance can optimize the nanoscale heat transport in the SOI FinFET device.

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

SummaryThis study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.

PBTI stress-induced 1/f noise in n-channel FinFET* *Project supported by the National Natural Science Foundation of China (Grant No. 61634008).

The influence of positive bias temperature instability (PBTI) on 1 / f noise performance is systematically investigated on n-channel fin field-effect transistor (FinFET). The FinFET with long and short channel (L = 240 nm, 16 nm respectively) is characterized under PBTI stress from 0 s to 104 s. The 1 / f noise features are analyzed by using the unified physical model taking into account the contributions from the carrier number and channel mobility fluctuations. The I d–V g, I d–V d, I g–V g tests are conducted to support and verify the physical analysis in the PBTI process. It is found that the influence of the channel mobility fluctuations may not be neglected. Due to the mobility degradation in a short-channel device, the noise level of the short channel device also degrades. Trapping and trap generation regimes of PBTI occur in high-k layer and are identified based on the results obtained for the gate leakage current and 1 / f noise.

Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET

In this paper, different physical models of single trap defects are considered, which are localized in the oxide layer or at the oxide–semiconductor interface of field effect transistors. The influence of these defects with different sizes and shapes on the amplitude of the random telegraph noise (RTN) in Junctionless Fin Field Effect Transistor (FinFET) is modelled and simulated. The RTN amplitude dependence on the number of single charges trapped in a single defect is modelled and simulated too. It is found out that the RTN amplitude in the Junctionless FinFET does not depend on the shape, nor on the size of the single defect area. However, the RTN amplitude in the subthreshold region does considerably depend on the number of single charges trapped in the defect.

A 4:1 multiplexer using low-power high-speed domino technique for large fan-in gates using FinFET

PurposeThis paper aims to propose a new fin field-effect transistor (FinFET)-based domino technique low-power series connected foot-driven transistors logic in 32 nm technology and examine its performance parameters by performing transient analysis.Design/methodology/approachIn the proposed technique, the leakage current is reduced at footer node by a division of current to improve the performance of the circuit in terms of average power consumption, propagation delay and noise margin. Simulation of existing and proposed techniques are carried out in FinFET and complementary metal-oxide semiconductor technology at FinFET 32 nm technology for 2-, 4-, 8- and 16-input domino OR gates on a supply voltage of 0.9 V using HSPICE.FindingsThe proposed technique shows maximum power reduction of 77.74% in FinFET short gate (SG) mode in comparison with current-mirror-based process variation tolerant (CPVT) technique and maximum delay reduction of 51.34% in low power (LP) mode in comparison with CPVT technique at a frequency of 100 MHz. The unity noise gain of the proposed circuit is 1.10× to 1.54× higher in comparison with different existing techniques in FinFET SG mode and 1.11× to 1.71× higher in FinFET LP mode. The figure of merit of the proposed circuit is up to 15.77× higher in comparison with existing domino techniques.Originality/valueThe research proposes a new FinFET-based domino technique and shows improvement in power, delay, area and noise performance. The proposed design can be used for implementing high-speed digital circuits such as microprocessors and memories.

Understanding the effect of confinement in scanning spreading resistance microscopy measurements

Scanning spreading resistance microscopy (SSRM) is a powerful technique for quantitative two-and three-dimensional carrier profiling of semiconductor devices with sub-nm spatial resolution. However, considering the sub-10 nm dimensions of advanced devices and the introduction of three-dimensional architectures like fin field effect transistor (FinFET) and nanowires, the measured spreading resistance is easily impacted by parasitic series resistances present in the system. The limited amount of material, the presence of multiple interfaces, and confined current paths may increase the total resistance measured by SSRM beyond the expected spreading resistance, which can ultimately lead to an inaccurate carrier quantification. Here, we report a simulation assisted experimental study to identify the different parameters affecting the SSRM measurements in confined volumes. Experimentally, the two-dimensional current confinement is obtained by progressively thinning down uniformly doped blanket silicon on insulator wafers using scalpel SSRM. The concomitant SSRM provides detailed electrical information as a function of depth up to oxide interface. We show that the resistance is most affected by the interface traps in case of a heterogeneous sample, followed by the intrinsic resistance of the current carrying paths. Furthermore, we show that accurate carrier quantification is ensured for typical back contact distances of 1 μm if the region of interest is at least nine times larger than the probe radius.

Electrothermal analysis of novel N-P-P FinFET with electrically doped drain: a dual material gate device for reliable nanoscale applications

In this paper, we offer a new structure of N+-P-P Fin Field Effect Transistor (FinFET) with a dual material gate in which the drain side P–N junction has been physically removed. The P-type drain consists of two parts, depletion region (DR) and electrically doped (ED) area, where the ED region is surrounded by an extra gate with optimized length and appropriate work function made of barium (B-gate). The ED region located under the B-gate is converted to N+ drain using the charged plasma (CP) concept to design the CP-FinFET. Improved ability to control the hot carrier effect by amending the critical electric field is the main idea of this work. The p-type depletion region (DR) created between the silicon active layer and electrically doped drain eliminates the gate-drain overlap and reduces the charge sharing and short channel effects (SCE). The modified electric field in the DR region offers advantages including improved hot-electron reliability and high-performance devices. Therefore, in the CP-FinFET the degradation mechanism improves due to the hot carrier effect (HCE) reduction. Indeed, the improvement in device performance is investigated using three-dimensional Atlas simulator with concentrating on the gate current, off-state current, reliability, electron temperature and gate induced drain leakage (GIDL). The comparison results demonstrate the superiority of the proposed structure as a high-efficiency device to design reliable Complementary metal–oxide–semiconductor circuits in nanoscale.