Cyclic approach for silicon nitride spacer etching in fin field-effect transistors and stacked nanowire devices

Abstract

Spacer etching in 3D CMOS technologies has become a very challenging step to be able to complete the etching while preserving channel and shallow trench insulation materials. The formation of parasitic spacers along fin sidewalls requires a lengthy overetch compared to conventional planar integrations to remove these undesired features, thereby drastically increasing the needed etching selectivities between silicon nitride, silicon (or SiGe), and silicon oxide. Based on an alternative etching chemistry, a new approach is assessed in this work, whose principle relies on selective passivation with an oxidelike material replacing the fluorine-containing organic layer encountered in dielectric etching with common fluorocarbons. Surface composition analyses demonstrate the preferential deposition on silicon with respect to silicon nitride yielding a high selectivity measured through etch rate tests on blanket films. The selectivity achieved is compatible with 3D CMOS spacer etching requirements. Despite the benefits shown by this alternative chemistry, some limitations prevent reaching the thorough elimination of parasitic spacer. A cyclic approach alternating selective passivation and nonselective etching is developed to overcome these limitations, which still provides effective silicon protection from etching. This cyclic sequence is evaluated on nanowire-type patterned structures and shows the complete removal of the parasitic spacer while providing a silicon loss of less than 2 nm. Work in development currently carries on to further improve this process and to fulfill all specifications for 3D CMOS spacer etching.