FIFO Buffers Research Articles

Buffered Simulation Games for Büchi Automata

Simulation relations are an important tool in automata theory because they provide efficiently computable approximations to language inclusion. In recent years, extensions of ordinary simulations have been studied, for instance multi-pebble and multi-letter simulations which yield better approximations and are still polynomial-time computable. In this paper we study the limitations of approximating language inclusion in this way: we introduce a natural extension of multi-letter simulations called buffered simulations. They are based on a simulation game in which the two players share a FIFO buffer of unbounded size. We consider two variants of these buffered games called continuous and look-ahead simulation which differ in how elements can be removed from the FIFO buffer. We show that look-ahead simulation, the simpler one, is already PSPACE-hard, i.e. computationally as hard as language inclusion itself. Continuous simulation is even EXPTIME-hard. We also provide matching upper bounds for solving these games with infinite state spaces.

Analysis of steady-state and transient delay in discrete-time single-arrival and batch-arrival systems

We perform an analysis of the transient delay in a discrete-time FIFO buffer with batch arrivals. As transient delay is an ambiguous concept, we first discuss different possible definitions of the term (delay of the kth customer, delay of a customer arriving at time t, etc.). In this paper, we focus on the analysis of the delay of a customer arriving in slot t, also sometimes called virtual delay in single-arrival systems. It turns out that the modeling in batch-arrival systems is more intricate. In analysis, we relate transient delay to transient unfinished work and characterize the latter. Some time-dependent as well as limiting steady-state delay measures are calculated. We also study a variation that is related to active probing measurements. A substantial part of the article finally focuses on some fundamental differences between alternative definitions of transient delay.

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs

This article describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook and is based on the existing Brook language. It allows system designers to express applications in a way that exposes parallelism, which can be exploited through hardware implementation. FPGA Brook supports replication, allowing parts of an application to be implemented as multiple hardware units operating in parallel. Hardware units are interconnected through FIFO buffers which use the small memory modules available in FPGAs. The FPGA Brook automated design flow uses a source-to-source compiler, developed as a part of this work, and combines it with a commercial behavioral synthesis tool to generate the hardware implementation. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results indicate that performance of many applications scales well with replication. Our benchmark applications also achieve significantly better results than corresponding implementations using a commercial behavioral synthesis tool. We conclude that using an automated design flow for implementation of streaming applications in FPGAs is a promising methodology.

PERFORMANCE INVESTIGATION OF RE-SHUFFLING PACKET ATTACK ON TRANSPORT LAYER PROTOCOL IN MANET

Over the past decade, the wireless world has experi enced significant developments. The emergence and pof radio frequency networking products, wireless devices lik e handheld, wearable and portable computers, Person al Digital Assistants (PDA)s, cellular phone have given rise to a kind of wireless revolution. A mobile ad hoc network is mu ch more assailable to attacks than a wired network due to its limited physical se curity, high mobility and lack of centralized admin istration. In this paper, we present and analyze the effects of re-shuffling att ack on TCP based mobile ad-hoc networks named as Pa cket Re-Shuffling. In the packet reshuffling attack the malicious node will rthe packets in its FIFO buffer before forwar ding them towards their destination. Due to the out of order delivery the rtime out of the packet is triggered a nd the source TCP and UDP has to retransmit the packet. In this way it also stops th e TCP to perform the congestion avoidance technique . A malicious node will always participate in route setup operations. For example, if source routing is employed, malicious nodes alw ays relay Route Request packets in order to have as many routes as possible flowing through themselves; if distance vector routing is employed, malicious nodes will also obey all control-plane protocol specifications . However, once a route is established, attacking n odes will thwart the end-to-end throughput of the flow via above mentioned attacks. The effect of the proposed attack is analyzed with the simulation results generated using the trial version of the simulator known as E xata Cyber 2.0. The simulation results are given in terms of metrics such as data flow throughput, Packet Retransmission, average end -to-end delay and packet delivery ratio. In this p aper, we are giving The study on UDP and TCP.

Research on the Parameter Model Simulation Based on Computer Simulation Basketball Match

With the development of computer hardware and software, the simulation of computer virtual simulation has been rapid development. The running process of computer simulation platform need to deal with massive data, and in general software testing technology can not meet the requirements. On the basis of this, an application computer virtual platforms parallel test method is proposed. Firstly, this paper gives a brief introduction for the process of computer simulation, and then the testing method can carry out software programming, it will realize the virtual process of serial FIFO buffer and register through reading and writing function. In order to develop basketball virtual platform as an example, the use of Simulink modules in MATLAB compare the serial and parallel testing of two testing methods used by software debugging time. Finally, we find that the parallel test is the best scheme of computer virtual platform software test, to provide theoretical reference for the design of software testing process.

Competitive buffer management with packet dependencies

We introduce the problem of managing a FIFO buffer of bounded space, where arriving packets have dependencies among them. Our model is motivated by the scenario where large data frames must be split into multiple packets, because maximum packet size is limited by data-link restrictions. A frame is considered useful only if sufficiently many of its constituent packets are delivered. The buffer management algorithm decides, in case of overflow, which packets to discard and which to keep in the buffer. The goal of the buffer management algorithm is to maximize throughput of useful frames. This problem has a variety of applications, e.g., Internet video streaming, where video frames are segmented and encapsulated in IP packets sent over the Internet. We study the complexity of the above problem in both the offline and online settings. We give upper and lower bounds on the performance of algorithms using competitive analysis.

The Design of Image Acquisition System Based on Contex-M3

A CMOS image acquisition system based on Contex-M3 is developed. In design STM32F103X is selected as the main controller, OV7670 is used for image sensors. In order to capture high-speed digital image, the FIFO buffer chip AL422B and SD Card under the control of the DMA are employed to directly transfer data. Moreover the SD card and 2.8 inch TFT LCD are selected to storage and display image data, respectively. Because of small size, low power, simple structure and low cost, the image acquisition system can provide an important reference value for development of similar system.

Enhanced Buffer Router Design in NOC

This paper presents an advance router design using enhanced buffer. The design provides advantages of both buffer and bufferless network for that two cross bar switches are used. The concept of virtual channel (VC) is eliminated from the previous design by using an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtual channel buffers (VCBs). This can be addressed by providing enhanced buffers on the bufferless link and creating two virtual networks. With this approach, VCBs act as distributed FIFO buffers. Without VCBs or VCs, deadlock prevention is achieved by duplicating physical channels. An enhanced buffer provides a function of hand shaking by providing a ready valid handshake signal and two bit storage. Through this design the power is saving to 18.98% and delay is reduced by 99.13% as compared with the generic router and the power is saving to 15.65% and delay is reduced to 97.88% as compared to virtual channel router. General Terms Router design, Virtual channel, Buffer architecture, Virtual Channel Allocation.

A column parity based fault detection mechanism for FIFO buffers

This paper presents a low cost fault detection mechanism for FIFO buffers. The scheme is based on column parity maintenance in a single register, which is updated by monitoring the values written to and read from the FIFO memory array. A non-zero column parity when the FIFO is empty, constitutes an indication of fault, and this property is exploited for fault detection. The technique has gains in area, power and critical path delay, at the expense of (1) greater detection latency, due to the need for the FIFO to become empty in order to assert a violation and (2) worse Silent Data Corruption (SDC) rate.

Queueing model analysis and scheduling strategy for embedded multi-core SoC based on task priority

Embedded devices have gradually increased the demand for computing performance. In recent years, researches have focused on ways to maximize the performance of embedded multi-core SoC when the hardware consumption is very limited. This paper presents a new queueing network model and performance analysis method for embedded multi-core SoC based on task handling mechanism with priority. To calculate the blocking probability and queueing situation of the implementation for every executing core, finite capacity holding nodes are added to the queueing model, and an equivalent queueing network model is obtained. An adaptive load scheduling algorithm is designed, and the main scheduler is real-time scheduling by blocking and queueing the situation of each core. Common priority FIFO buffer, high-priority FIFO buffer queue, and semi-global FIFO buffer queue are a reasonable distribution. Finally, the approximate iterative algorithm is proposed for evaluating system performance. The experimental results indicate that the adaptive scheduling algorithm significantly improves the balance of task assignment.

Combined Analysis of Transient Delay Characteristics and Delay Autocorrelation Function in the G e o X / G /1 Queue

We perform a discrete-time analysis of customer delay in a buffer with batch arrivals. The delay of the kth customer that enters the FIFO buffer is characterized under the assumption that the numbers of arrivals per slot are independent and identically distributed. By using supplementary variables and generating functions, z-transforms of the transient delays are calculated. Numerical inversion of these transforms lead to results for the moments of the delay of the kth customer. For computational reasons k cannot be too large. Therefore, these numerical inversion results are complemented by explicit analytic expressions for the asymptotics for large k. We further show how the results allow us to characterize jitter-related variables, such as the autocorrelation of the delay in steady state.

Experimental Demonstration of an Operand Routing Network Prototype Employing Clock Control and Data Synchronization Scheme

We have previously proposed a clock distribution and data synchronization scheme to address a problem of jitter accumulated in Large Scale SFQ circuits such as Reconfigurable Data Paths processor (RDP). The RDP is divided into several stages clocked separately by an external jitter free system clock and FIFO buffers and clock controllers between the stages are used to synchronize data. In this paper we present architecture and experimental results of an RDP prototype that employed Operand Routing Network (ORN) and clock control and data synchronization scheme designed for ISTECSRL 10 kA/cm 2 advanced process. The circuit consisted of the ORN with 3 data inputs and maximum connection length equal to 1, three 8-bit input and six 10-bit output dual FIFO buffers, a 3-bit controller, a ladder type high frequency clock signal generator and six 8-bit output shift registers. Total it employed 6536 Josephson junctions and required a bias current of 0.74 A. The prototype was successfully tested at the frequencies up to 48 GHz.

A near-optimal memoryless online algorithm for FIFO buffering two packet classes

We consider scheduling packets with values in a capacity-bounded buffer in an online setting. In this model, there is a buffer with limited capacity B. At any time, the buffer cannot accommodate more than B packets. Packets arrive over time. Each packet has a non-negative value. Packets leave the buffer only because they are either sent or dropped. Those packets that have left the buffer will not be reconsidered for delivery any more. In each time step, at most one packet in the buffer can be sent. The order in which the packets are sent should comply with the order of their arrival time. The objective is to maximize the total value of the packets sent in an online manner. In this paper, we study a variant of this FIFO buffering model in which a packet’s value is either 1 or α>1. We present a deterministic memoryless 1.304-competitive algorithm. This algorithm has the same competitive ratio as the one presented in Lotker and Patt-Shamir [Z. Lotker, B. Patt-Shamir, Nearly optimal FIFO buffer management for DiffServ, in: Proceedings of the 21st Annual ACM Symposium on Principles of Distributed Computing, PODC, 2002, pp. 134–142; Z. Lotker, B. Patt-Shamir, Nearly optimal FIFO buffer management for DiffServ, Computer Networks 17 (1) (2003) 77–89]. However, our algorithm is simpler and does not employ any marking bits. The idea used in our algorithm is novel and different from all previous approaches that have been applied for the general model and its variants. We do not proactively preempt one packet when a new packet arrives. Instead, we may preempt more than one 1-value packet at the time when the buffer contains sufficiently many α-value packets.

Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor

We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm2 and advanced 10 kA/cm2 processes and successfully tested at high speed.

Small trusted primitives for dependable systems

Secure, fault-tolerant distributed systems are difficult to build, to validate, and to operate. Conservative design for such systems dictates that their security and fault tolerance depend on a very small number of assumptions taken on faith; such assumptions are typically called the "trusted computing base" (TCB) of a system. However, a rich trade-off exists between larger TCBs and more secure, more faulttolerant, or more efficient systems. In our recent work, we have explored this trade-off by defining "small," generic trusted primitives--for example, an attested, monotonically sequenced FIFO buffer of a few hundred machine words guaranteed to hold appended words until eviction and showing how such primitives can improve the performance, fault tolerance, and security of systems using them. In this article, we review our efforts in generating simple trusted primitives such as an attested circular buffer (called Attested Appendonly Memory), and an attested human activity detector. We describe the benefits of using these primitives to increase the fault-tolerance of replicated systems and archival storage, and to improve the security of email SPAM and click-fraud prevention systems. Finally, we share some lessons we have learned from this endeavor.

Learning Communicating Automata from MSCs

This paper is concerned with bridging the gap between requirements and distributed systems. Requirements are defined as basic message sequence charts (MSCs) specifying positive and negative scenarios. Communicating finite-state machines (CFMs), i.e., finite automata that communicate via FIFO buffers, act as system realizations. The key contribution is a generalization of Angluin's learning algorithm for synthesizing CFMs from MSCs. This approach is exact-the resulting CFM precisely accepts the set of positive scenarios and rejects all negative ones-and yields fully asynchronous implementations. The paper investigates for which classes of MSC languages CFMs can be learned, presents an optimization technique for learning partial orders, and provides substantial empirical evidence indicating the practical feasibility of the approach.

On the verification problem for weak memory models

We address the verification problem of finite-state concurrent programs running under weak memory models. These models capture the reordering of program (read and write) operations done by modern multi-processor architectures for performance. The verification problem we study is crucial for the correctness of concurrency libraries and other performance-critical system services employing lock-free synchronization, as well as for the correctness of compiler backends that generate code targeted to run on such architectures. We consider in this paper combinations of three well-known program order relaxations. We consider first the "write to read" relaxation, which corresponds to the TSO (Total Store Ordering) model. This relaxation is used in most hardware architectures available today. Then, we consider models obtained by adding either (1) the "write to write" relaxation, leading to a model which is essentially PSO (Partial Store Ordering), or (2) the "read to read/write" relaxation, or (3) both of them, as it is done in the RMO (Relaxed Memory Ordering) model for instance. We define abstract operational models for these weak memory models based on state machines with (potentially unbounded) FIFO buffers, and we investigate the decidability of their reachability and their repeated reachability problems. We prove that the reachability problem is decidable for the TSO model, as well as for its extension with "write to write" relaxation (PSO). Furthermore, we prove that the reachability problem becomes undecidable when the "read to read/write" relaxation is added to either of these two memory models, and we give a condition under which this addition preserves the decidability of the reachability problem. We show also that the repeated reachability problem is undecidable for all the considered memory models.

Capturing the object behaviour for storage system evaluation

In this paper, we present a kind of distributed tracing system for evaluating the performance of object storage system. The tracing build on the object-based Lustre file system can capture the object information synchronously from three subsystems of Lustre cluster file system. To improve I/O performance and efficiency, we utilise a queue and a FIFO buffer area to store trace data which is finally written out to a trace file by an output driver. In particular, we use some database tables to save the final integrated traces for convenient post-analysis. We have implemented and evaluated a prototype object tracing system on Linux which patched with Lustre 1.4.5 custom kernel patches. Our evaluation shows a low overhead tracing system.

Design of the License Plate Recognition Platform Based on the DSP Embedded System

The license plate recognition system (LPRS) is a very important development direction of the intelligent transportation systems (ITS). With the development of the society and the enhancement of human living level, the amount of vehicle increases continually and the traffic status is deteriorating gradually, which brings large pressures for the society and the environment. The increasingly crowded city traffic needs more advanced and effective traffic management and control. It has been an important research direction to utilize the license plate recognition technology to enhance the management level and the traffic efficiency, and implement safe intelligent transportation management. In this article, the design, implementation and optimization of the DSP license plate recognition system which takes the TMS320C6201 of TI Corporation as the core chip were introduced. In this system, the video frequency (VF) decoding chip first translates the analog TV image signals obtained from CCD into the digital image signals which are inputted into DSP through FIFO buffer by the control of CPLD, and then aiming at the image, DSP performs the license plate positioning, the license plate character segmentation, the license plate character identification, the optical aberrance emendation, the nonlinear emendation of speed error and other algorithm operations to obtain the result of the license plate identification.

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding

This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.