FIFO Buffers Research Articles

A hierarchy of communication models for Message Sequence Charts

In a Message Sequence Chart (MSC) the dynamical behaviour of a number of cooperating entities is depicted. An MSC defines a partial order on the communication events between these entities. This order determines the physical architecture needed for implementing the specified behaviour, such as a FIFO buffer between each of the entities. In a systematic way, we define 50 communication models for MSC and we define what it means for an MSC to be implementable by such a model. Some of these models turn out to be equivalent, in the sense that they implement the same class of MSCs. After analysing the notion of implementability, only ten classes remain, for which we develop a hierarchy. We also develop algorithms to check whether a given MSC belongs to such a class.

Effective bandwidth and associated CAC procedure for traffic streams multiplexed over a VBR link

In this paper we introduce the definition of the effective bandwidth for traffic streams that are multiplexed over a VBR link. We assume an arbitrary traffic mix multiplexed into a FIFO buffer, which has a service rate, regulated by VBR traffic parameters as opposed to the traditional CBR server capacity. In order to analytically obtain the generalized effective bandwidth we define an equivalent queuing model, which reduces the problem of the variable service rate multiplexer to a constant rate server. Following the Large Deviation Analysis of our equivalent queuing model we derive the effective bandwidth in terms of VBR link parameters. One of the appealing features of our method is that any dimensioning, resource allocation schemes that are based on the effective bandwidth concept but originally have been devised for CBR links can be easily extended to be applicable for VBR links as well. For example, one can easily build a Connection Admission Control (CAC) algorithm for a VBR link by reusing the existing methods based on the effective bandwidth concept. In this paper we also give an example for a CAC algorithm and for other practical application scenarios.

Zero dead time spectroscopy without full charge collection

The Savannah River Technology Center has built a remote gamma monitoring instrument which employs data sampling techniques rather than full charge collection to perform energy spectroscopy without instrument dead time. The raw, unamplified anode output of a photomultiplier tube is directly coupled to the instrument to generate many digital samples during the charge collection process, so that all pulse processing is done in the digital domain. The primary components are a free running, 32 MSPS, 10-bit A/D, a field programmable gate array, FIFO buffers, and a digital signal processor (DSP). Algorithms for pulse integration, pile-up rejection, and other shape-based criteria are being developed in DSP code for migration into the gate array. Spectra taken with a 2 in NaI(Tl) detector have been obtained at rates as high as 59 000 counts per second without dead time with peak resolution at 662 keV measuring 7.3%.

A fair buffer allocation scheme

An appropriate service for data traffic in Asynchronous Transfer Mode (ATM) networks requires large buffers in network nodes. However, large buffers without a proper allocation scheme may lead to an unsatisfactory quality of service. Most present allocation schemes either necessitate a complicated queueing system or they do not offer a sufficient fairness. This paper describes a rather simple buffer management scheme that results in fair allocation of bandwidth among competing connections by using only a FIFO buffer. The performance and fairness of the allocation scheme has been analysed by means of a simulation program.

The ready-to-go virtual circuit protocol: a loss-free protocol for multigigabit networks using FIFO buffers

The ready-to-go virtual circuit protocol (or RGVC) is an immediate transmission protocol, in which the source need not wait for an end-to-end roundtrip delay for reservations to be made before transmitting the data. The protocol is designed to handle the lossless transport of ABR traffic, and will be used in the 40 Gb/s Thunder and Lightning testbed being prototyped at the University of California at Santa Barbara (UCSB). An important advantage of the RGVC protocol over previous connection and flow control protocols is that it is suitable for networks in which the switches use FIFO buffers that are shared by multiple sessions. The RGVC protocol ensures lossless communication by coupling link capacity with buffer space, so that when a portion of a buffer at a node is occupied, a proportional fraction of the incoming capacity to that buffer is frozen. Given the constraints on the frozen capacity, an algorithm is executed at each node to allocate the transmission rate to each FIFO buffer so as to maximize capacity utilization. The requirement that the protocol operate with FIFO buffers at the network nodes poses some unique challenges in the design that are not present in rate- and credit-based schemes. Briefly, since several sessions share a common FIFO buffer, per-VC flow control is no longer possible so control over the rate of an individual session is lost. Also, since the contents of the buffers change dynamically, the buffer composition becomes difficult to determine. For the rate-allocation algorithm of the RGVC protocol to be executed, however, the contents of the FIFO buffers at a node must be known, To implement the bookkeeping required, we present two schemes: the measurement-based scheme, where the bookkeeping function is implemented via measurements, done essentially in hardware; and the estimation-based scheme, where the bookkeeping is done analytically via the exchange of control packets between nodes.

8 Gbit/s CMOS interface for parallel fibre-opticinterconnects

The authors demonstrate an 8 Gbit/s CMOS link interface designed for use with parallel fibre-optic interconnect technology. The link interface is implemented in 0.8 /spl mu/m CMOS and consists of eight data channels and one frame control channel each operating at 1 Gbit/s along with a full-speed 1 GHz clock channel. The chip also provides dual-ported FIFO buffers for interface to a host computer.

Linearizable counting networks

The counting problem requires n asynchronous processes to assign themselves successive values. A solution is linearizable if the order of the values assigned reflects the real-time order in which they were requested. Linearizable counting lies at the heart of concurrent time-stamp generation, as well as concurrent implementations of shared counters, FIFO buffers, and similar data structures. We consider solutions to the linearizable counting problem in a multiprocessor architecture in which processes communicate by applying read-modify-write operations to a shared memory. Linearizable counting algorithms can be judged by three criteria: the memory contention produced, whether processes are required to wait for one another, and how long it takes a process to choose a value (the latency). A solution is ideal if it has low contention, low latency, and it eschews waiting. The conventional software solution, where processes synchronize at a single variable, avoids waiting and has low latency, but has high contention. In this paper we give two new constructions based on counting networks, one with low latency and low contention, but that requires processes to wait for one another, and one with low contention and no waiting, but that has high latency. Finally, we prove that these trade-offs are inescapable: an ideal linearizable counting algorithm is impossible. Since ideal non-linearizable counting algorithms exist, these results establish a substantial complexity gap between linearizable and non-linearizable counting.

Low power dual-port CMOS SRAM macro design

A novel low power dual-port CMOS SRAM structure is described. The inherent low power advantage is obtained by using current-mode rather than voltage-mode signal transmission. The design of this new dual-port memory cell and current-mode sense amplifier is based on 0.5 µm, 5 V CMOS logic process technology. HSPICE simulations show that the circuits can operate at high speed even if the supply voltage is reduced to 2 V. The dual-port memory cell is most suitable for the design of FIFO buffers.

High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits

New high-performance building blocks for two-phase micropipelines are presented, and pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for datapath storage are developed in place of traditional capture-pass or transmission gate latches. A DETDFF FIFO buffer implementation is compared with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor and also with Sutherland's original two-phase micropipeline. All three designs were simulated in the MOSIS 1.2 µm CMOS process under the worst-case process corner with a 4.6 V power supply and at 100°C. The authors' SPICE simulations show that the DETDFF design has 70% and 150% higher throughput than Day and Woods' and Sutherland's, respectively. This higher throughput is due to latching the data on both edges of the latch control, removing the need for a reset phase and simplifying the control structures. In addition, two commonly used micropipeline event-control structures, the select and toggle elements, are implemented using the extended-burst-mode 3D synthesis system. Detailed simulations demonstrate that our implementations are up to 50% faster than traditional implementations. This speed advantage can be primarily attributed to careful applications of generalised C-elements rather than discrete basic gates.

Unreliable Channels Are Easier to Verify Than Perfect Channels

We consider the problem of verifying correctness of finite state machines that communicate with each other over unbounded FIFO channels that are unreliable. Various problems of interest in verification of FIFO channels that can lose messages have been considered by Finkel and by Abdulla and Jonsson. We consider, in this paper, other possible unreliable behaviors of communication channels, viz., (a) duplication and (b) insertion errors. Furthermore, we also consider various combinations of duplication, insertion, and lossiness errors. Finite state machines that communicate over unbounded FIFO buffers are a model of computation that forms the backbone of the ISO standard protocol specification languages Estelle and SDL. While the assumption of a perfect communication medium is reasonable at the higher levels of the OSI protocol stack, the lower levels have to deal with an unreliable communication medium; hence our motivation for the present work. The verification problems that are of interest arereachability,unboundedness,deadlock, andmodel-checking against CTL*. All of these problems are undecidable for machines communicating over reliable unbounded FIFO channels. So it is perhaps surprising that some of these problems become decidable when unreliable channels are modeled. The contributions of this paper are (a) an investigation of solutions to these problems for machines with insertion errors, duplication errors, or a combination of duplication, insertion, and lossiness errors, and (b) a comparison of the relative expressive power of the various errors.

ARQ protocols for high speed hardware implementation

In order to fully exploit high speed communication channels the processing burden at the end points must be reduced. One way in which this can be done is by shifting the implementation of protocols from software to specialized, dedicated hardware. This process is made easier if the protocols are designed with hardware implementation in mind. In this paper we consider a family of ARQ protocols that can be implemented through relatively simple hardware-one or more FIFO buffers and some limited state information. With a single FIFO buffer the protocol is identical to a regular Go-Back-N. By increasing the number of FIFO buffers we can reach a full selective repeat. The main result is to show that, for typical error rates, performance close to selective repeat can be obtained with two or three FIFO buffers. The family of protocols is described in detail followed by throughput analysis. For the two buffer case a closed-form solution is obtained while for other cases simulation results are given.

Evaluation of sequential-in-random-out memory device

The buffering of data is a potential bottleneck to performance. In general, the buffer can be implemented either by FIFO or dual-port RAM, which are both two-port memory devices. In the Letter a classification of buffers is proposed. According to the classification, a new two-port memory device with the sequential-in-random-out feature is introduced. Simulation results show that 45% time, at most, could be saved, as compared to a FIFO buffer.

Duplication, insertion and lossiness errors in unreliable communication channels

We consider the problem of verifying correctness of finite state machines that communicate with each other over unbounded FIFO channels that are unreliable. Various problems regarding verification of FIFO channels that can lose messages have been considered by Finkel [10], and by Abdulla and Johnson [1, 2]. We consider, in this paper, other possible unreliable behaviors of communication channels, viz. (a) duplication and (b) insertion errors. Furthermore, we also consider various combinations of duplication, insertion and lossiness errors.Finite state machines that communicate over unbounded FIFO buffers is a model of computation that forms the backbone of ISO standard protocol specification languages Estelle and SDL. While an assumption of a perfect communication medium is reasonable at the higher levels of the OSI protocol stack, the lower levels have to deal with an unreliable communication medium; hence our motivation for the present work.The verification problems that are of interest are reachability, unboundedness, deadlock , and model-checking against CTL . All of these problems are undecidable for machines communicating over reliable unbounded FIFO channels. So, it is perhaps surprising that some of these problems become decidable when unreliable channels are modeled. The contributions of this paper are: (a) An investigation of solutions to these problems for machines with insertion errors, duplication errors, or a combination of duplication, insertion and lossiness errors, and (b) A comparison of the relative expressive power of the various errors.

Multichannel real-time data acquisition system using dual ported FIFO buffers

In contrast to real-time data acquisition systems employing a minicomputer with a real-time multiprogramming operating system, this paper describes the design and development of a high throughput data acquisition system using an IBM compatible PC/AT, high speed sampling A/D converter, and dual ported FIFO RAM buffers, in the MS-DOS environment. Data acquisition software is developed in Turbo Pascal with a few in-line machine language procedures.

Effective bandwidth allocation and buffer dimensioning in ATM based networks with priorities

Abstract We consider an ATM multiplexer with several FIFO buffers operating in the non-preemptive priority regime. Each connection or type of traffic (e.g. connectionless services) is allocated to one priority characterized by its grade of service constraints. Under very general assumptions we derive a model for buffer dimensioning and effective bandwidth allocation. The approach is based on upper bounds for grade of service measures (cell blocking, average cell delay) expressed in terms of performance of independent non-priority multiplexers (one for each priority). It is assumed that a model for buffer dimensioning and effective bandwidth allocation in a non-priority multiplexer with one FIFO queue is available. the important features of the approach are illustrated by means of numerical examples. The efficiency of the approach is also discussed.

An error-controlled approximate analysis of a stochastic fluid flow model applied to an ATM multiplexer with heterogeneous on-off sources

The stochastic fluid flow approach is applied to the analysis of the cell loss performance of an ATM multiplexer. The input traffic stream offered to the multiplexer is the superposition of heterogeneous on-off sources with independent and exponentially distributed on and off times. The focus is on the numerical investigation of the steady-state behavior of models involving very large state spaces. To this end, an efficient algorithm for the evaluation of tight upper and lower bounds of the cell loss probability is developed. The algorithm allows a significant reduction of the computational burden, while yielding a guaranteed overestimate of the error implied by the proposed approximation of the cell loss probability. Numerical results are presented both to assess the tightness of the proposed bounds and to gain insight into the behavior of heterogeneous traffic mixes. The main conclusion, from the multiplexer performance evaluation point of view, is that it is not convenient to mix very different traffic streams in a completely shared FIFO buffer, without some kind of control.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An integrated high performance Fastbus slave interface

Abstract A high performance Fastbus slave interface ASIC is presented. The Fastbus slave integrated circuit (FASIC) is a programmable device, enabling its direct use in many different applications. The FASIC acts as an interface between Fastbus and a “standard” processor/memory bus. It can work stand-alone or together with a microprocessor. A set of address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/s to Fastbus can be obtained using an internal FIFO buffer in the FASIC.

A CAMAC timing module for the use with high energy resolution detectors

A CAMAC module which measures event times with a resolution of 10 ns continuously over a period of 32.6 days has been built. The event times are stored in a deep buffer memory in form of 48-bit data words. The pulse amplitude of each event can be measured concurrently in a high resolution ADC and stored in another FIFO buffer memory. These amplitudes are tagged with a flag to correlate time with amplitude value unambiguously. In spite of the high operating frequency of 100 MHz necessitating the use of ECL counters, the module is compact (single-width) thanks to the use of TTL registers for the intermediate storage of the 48-bit time-word. The setup and testing of the modules with a NaI-pair spectrometer used in the GALLEX solar neutrino experiment is described. Other possible applications of the module in the field of non-accelerator particle physics are also mentioned.

Processor arrays for matrix triangularisation with partial pivoting

Two processor arrays for triangularisation of dense matrices using Gaussian elimination with partial pivoting are synthesised from the algorithm description. These arrays consist of processing modules with FIFO buffers and manifest local intermodule communications. Both the one- and two-dimensional arrays process an n × n matrix in O(n2) time, while the last allows an O(n) block pipelining period. The estimations of the processing time on the 1-D array and the block pipelining period on the 2-D array are identical to those for the numerically unstable case of Gaussian elimination without pivoting.

A data collection system for protein crystallography with area-sensitive proportional counters

To take full advantage of the capabilities of an area-sensitive electronic detector for x-ray crystallography, data analysis and reduction has to be performed in parallel to the data collection. A data collection system is described that makes extensive use of computer modules for the VME bus. The data acquisition electronics is embedded in the computer system that analyzes the diffraction pictures so as to keep data transfer time short. It is based on an intelligent computer module allowing us to add the electronic hardware necessary for our specific application. Using a fast FIFO buffer we can collect 24-bit-wide data words at an average rate of almost 300 kHz with a dead time τD of 100 ns between successive events.