FIFO Buffers Research Articles

Low-cache high-deterministic mesochronous dual-clock FIFO buffer

Low-cache high-deterministic mesochronous dual-clock FIFO buffer

FPGA implementation of sobel edge detection algorithm

Sobel Edge detection algorithm is used to extract the edges (region of maximum variation) from an image. It is based on the concept that the edges of an image contains maximum information whose computation depends on multipliers and square root. As multipliers consume more logic, a modified sobel edge detection algorithm which does not employ multipliers and square root function is proposed. A mathematical model of the proposed sobel edge algorithm was first developed and MATLAB was used to verify the model. On comparing with the original model, the proposed model has a SSIM of 96.43%. To analyse the hardware complexity, Verilog model of the modified sobel edge detection algorithm was developed using Quartus II. The chosen evaluation board is Cylone III FPGA EP3C120F780. The performance metrics such has Logic Elements utilization, Power dissipation and Maximum Operating Frequency were obtained. Open-Source toolchain (Yosys, OpenVPR, and Google Skywater 130nm PDK) was used to obtain the RTL Netlist and Synthesis reports. Verilog Modules for the Camera (CMOS OV7670) interface and FIFO Buffer were synthesized. The modified algorithm was integrated with them. An HSMC (HSMB) breakout board was connected to the FPGA Development board to increase the number of I/O ports. Thus in real time, the proposed modified Sobel Edge detection system can be used as a pre-processor to reduce the amount of computations and power consumption.

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

In recent years, the adoption of FPGAs in datacenters has increased, with a growing number of users choosing High-Level Synthesis (HLS) as their preferred programming method. While HLS simplifies FPGA programming, one notable challenge arises when scaling up designs for modern datacenter FPGAs that comprise multiple dies. The extra delays introduced due to die crossings and routing congestion can significantly degrade the frequency of large designs on these FPGA boards. Due to the gap between HLS design and physical design, it is challenging for HLS programmers to analyze and identify the root causes, and fix their HLS design to achieve better timing closure. Recent efforts have aimed to address these issues by employing coarse-grained floorplanning and pipelining strategies on task-parallel HLS designs where multiple tasks run concurrently and communicate through FIFO stream channels. However, many applications are not streaming friendly and many existing accelerator designs heavily rely on buffer channel based communication between tasks. In this work, we take a step further to support a task-parallel programming model where tasks can communicate via both FIFO stream channels and buffer channels. To achieve this goal, we design and implement the PASTA framework, which takes a large task-parallel HLS design as input and automatically generates a high-frequency FPGA accelerator via HLS and physical design co-optimization. Our framework introduces a latency-insensitive buffer channel design, which supports memory partitioning and ping-pong buffering while remaining compatible with vendor HLS tools. On the frontend, we provide an easy-to-use programming model for utilizing the proposed buffer channel; while on the backend, we implement efficient placement and pipelining strategies for the proposed buffer channel. To validate the effectiveness of our framework, we test it on four widely used Rodinia HLS benchmarks and two real-world accelerator designs and show an average frequency improvement of 25%, with peak improvements of up to 89% on AMD/Xilinx Alveo U280 boards compared to Vitis HLS baselines.

An enhanced approach towards improving the performance of embedding memory management units into Network-on-Chip

Network-on-Chip (NoC) initiates the design procedure of interconnection network into SoC - System-on-Chip. The current technique overcomes the drawbacks of traditional bus-based SoC, for instance, poor scalability, small-link bandwidth, and large delay. The network-on-Chip systems required minimum buffering space and low-latency requirements. Here, the FIFO buffer is utilized as a virtual channel to evade deadlock issues and thus enhances throughput. The current research focused on an enhanced toward improving Embedding-Memory-management- Units performance into Network-on-Chip. Here, the 3D NoC was considered in the study for Noc improvement and has achieved high performance. Further, A first-in-first-out (FIFO) buffer was used in NoC routers to store the data packets temporarily. Eventually, the RAM -random access memory was proposed that serves as a link between the crossbar switch and the input ports. The simulation result of the current research results in only 0 to 16 memory for data storage in a stack out of 64, with the almost empty signal being high.

Introduction and application analysis of FIFO-related methods

In this paper, an improved method of using binary pointers is proposed based on the analysis of the basic principles and structure of FIFO. The paper also presents a high-speed data acquisition system based on STM32 with an asynchronous FIFO designed to solve the insufficient data acquisition speed and high-power consumption problems of fiber-optic grating sensors in the electrical industry. The use of binary pointers significantly improves the processing speed and reduces the power consumption of the FIFO, thus improving the overall efficiency.In addition, the paper introduces the use of a field-programmable gate array (FPGA) design as the control core of a color sorter system. This overcomes the drawbacks of processor-based multi-channel color sorters, including low delay accuracy, poor consistency, and persistent signal loss. The FPGA offers superior performance due to its parallel computing capabilities and flexibility in algorithm implementation, making it ideal for high-performance applications such as color sorting systems.The color sorter system designed using FPGA technology is capable of sorting different materials based on color, shape, and size. The system's superior performance is due to the use of an asynchronous FIFO buffer that enables real-time color recognition and processing. By incorporating the FIFO buffer, the system can achieve high processing speeds, consistent color recognition, and minimal signal loss, providing a valuable solution for applications requiring high-precision color sorting.

SplitZNS: Towards an Efficient LSM-Tree on Zoned Namespace SSDs

The Zoned Namespace (ZNS) Solid State Drive (SSD) is a nascent form of storage device that offers novel prospects for the Log Structured Merge Tree (LSM-tree). ZNS exposes erase blocks in SSD as append-only zones, enabling the LSM-tree to gain awareness of the physical layout of data. Nevertheless, LSM-tree on ZNS SSDs necessitates Garbage Collection (GC) owing to the mismatch between the gigantic zones and relatively small Sorted String Tables (SSTables). Through extensive experiments, we observe that a smaller zone size can reduce data migration in GC at the cost of a significant performance decline owing to inadequate parallelism exploitation. In this article, we present SplitZNS, which introduces small zones by tweaking the zone-to-chip mapping to maximize GC efficiency for LSM-tree on ZNS SSDs. Following the multi-level peculiarity of LSM-tree and the inherent parallel architecture of ZNS SSDs, we propose a number of techniques to leverage and accelerate small zones to alleviate the performance impact due to underutilized parallelism. (1) First, we use small zones selectively to prevent exacerbating write slowdowns and stalls due to their suboptimal performance. (2) Second, to enhance parallelism utilization, we propose SubZone Ring, which employs a per-chip FIFO buffer to imitate a large zone writing style; (3) Read Prefetcher, which prefetches data concurrently through multiple chips during compactions; (4) and Read Scheduler, which assigns query requests the highest priority. We build a prototype integrated with SplitZNS to validate its efficiency and efficacy. Experimental results demonstrate that SplitZNS achieves up to 2.77× performance and reduces data migration considerably compared to the lifetime-based data placement. 1

Performance Analysis of an Efficient Router using X Y Algorithm

As more and more functions are expected to be performed by a single electronic device (such as a smartphone, smart television, etc.), the need to have more and more components on SoC is increasing, posing new difficulties for NoC. The majority of NoC designs utilise mesh, torus, or other topologies to ensure a robust router. Most solutions, however, fall short when it comes to addressing key issues like throughput, area overhead, and latency, as well as QoS and congestion. The current paper proposes a concept for a reconfigurable router that can be used in No C settings. For the suggested router's design, we use Verilog, formal language for describing hardware (Verilog HDL). The four-channel router presented here has an east-west-north-south orientation and a crossbar switch connecting the two pairs of channels. Each channel consists of a multiplexer and a FIFO buffer. The input and output are handled by multiplexers, and the data is stored in FIFO buffers. The FIFO and multiplexer architectures for the south channel are developed initially. Afterwards the remaining three channels and the crossbar switch are made. Routers use channels, FIFO buffers, multiplexers, and crossbar switches in their overall design. Simulating the proposed design in Modelsim and obtaining the RTL view in Xilinx ISE 14.0 are the two primary methods of approaching this problem. The suggested reconfigurable router's power consumption is greatly reduced by employing the Power gating technique.. The XPower Analyzer application is used to determine the total power. As demonstrated by the findings obtained, the proposed design uses less energy than conventional reconfigurable routers.

A high-performance energy efficient packet classification design on FPGA

One of the most crucial thing to safeguard the network against malicious activities is security and the network devices must be able to classify packets. The firewall applications benefit greatly from the architecture of the packet classification engine that is given in this research work. A tree-based approach is used to systematically analyze each field in a packet header, leading to a more secure system. The Packet Classification Engine (PCE) is configured to evaluate Ethernet packets based on the source IP address, destination IP address, source port, destination port, and protocol aspects in the packet header. The PCE shows that the typical clock frequency from input to output is 13 clocks per second. The architecture is extremely rapid, reliable, and adaptable and can make good use of the tree based algorithm's advantages. The proposed architecture has achieved high throughput of 538 MPPS with less energy of 10.6 nJ at low latency of 62 ns. The PCE must have a rapid and reliable FIFO buffer to work effectively. A FPGA (Field Programmable Gate Array) device is being utilized to filter Ethernet packets using the proposed PCE.

A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock

This brief presents a low-cost blind oversampling CDR (Clock Data Recovery) architecture that obviates the need of a dedicated clock generator or oversampling clock at the receiver end of a high-speed serial link. The proposed CDR reuses an existing at-speed clock available in the system. It deploys a sampler circuit at the input coupled to a data storage and control block that frames the serial input into a parallel output data frame along with the recovered clock. The all-digital CDR algorithm tracks clock impairments and takes appropriate action when UI (Unit Interval) boundaries are violated. Samples obtained at non-uniform time stamps near rise & fall clock edges are used to determine valid data captures. Unlike conventional oversampling CDRs, it achieves high jitter tolerance (JTOL) without storing and post processing multiple data word samples. The absence of a FIFO and elastic buffer in the design greatly reduces design size. As a result, the proposed technique achieves low power, wide-range operation with minimal hardware overhead and design implementation effort while delivering performances at par with conventional approaches. A 2Gbps CDR design in 28nm technology is demonstrated with digital area 0.00063mm2 and power 0.88mW.

Compatibility checking for cyber‐physical systems based on microservices

AbstractMicroservices architecture provides a promising solution for developing sustainable cyber‐physical systems (CPSs). However, checking the compatibility of CPSs over a set of microservices communicating asynchronously via unbounded buffers are undecidable due to their infinite state spaces. In this article, we propose a new approach for checking the compatibility of CPSs with infinite state spaces without restricting the size of buffers or the number of communication cycles. First, we integrate CPSs with microservice architecture and design the system architecture for building CPSs over a set of cyber‐physical microservices with unbounded buffers. Second, we model CPSs composed of asynchronously communicating cyber‐physical microservices via FIFO buffers as labelled transition systems. Third, we adopt the stability notion and present a sufficient condition for checking the unspecified receptions of CPSs through stability checking. Finally, we implement our approach in Process Analysis Toolkit for automatic compatibility checking and conduct experiments to show our approach is effective and efficient.

FPGA friendly NoC simulation acceleration framework employing the hard blocks

A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures.

Compatibility checking for asynchronously communicating software

• Inter-operability of distributed systems. • Asynchronous operational semantics using FIFO buffers. • Decidability of synchronizability and wellformedness. • Refinement based proofs and model checking of distributed systems' compatibility. • Tool support. Compatibility is a crucial problem that is encountered while constructing new software by reusing and composing existing components. A set of software components is called compatible if their composition preserves certain properties, such as deadlock freedom. However, checking compatibility for systems communicating asynchronously is an undecidable problem, and asynchronous communication is a common interaction mechanism used in building software systems. A typical approach in analyzing such systems is to bound the state space. In this article, we propose a different approach and do not impose any bounds on the number of participants or the sizes of the message buffers. Instead, we present a sufficient condition for checking compatibility of a set of asynchronously communicating components. Our approach relies on the synchronizability property which identifies systems for which interaction behavior remains the same when asynchronous communication is replaced with synchronous communication. Using the synchronizability property, we can check the compatibility of systems with unbounded message buffers by analyzing only a finite part of their behavior. We have implemented a prototype tool to automate our approach and we have applied it to many examples.

Hardware and software of behavior experiments

One of the areas of experimental physiological research is the study of pain. One of the common pain stimuli used in many laboratories in the world is electric current. In behavioral experiments, a common way of organizing an electrical impact on a moving laboratory animal is to apply electrical voltage to the metal bars of the experimental cage floor. When the animal locks bars with different potential, it receives an electrical shock. It is desirable during the experiment to change the polarity of the electric potential on the bars of the lattice, in order to minimize the ability of the animal to avoid electrical exposure, located on the bars with the same electric potential. The sequence of polarity reversal on metal bars of the cage floor was organized in such a way that not a single pair of bars had the same polarity during the supply cycles of electric current pulses and the animal received an electrical shock at least once per cycle when it closed any pair of bars. Experimental techniques are known in which the voltage applied to the cage floor between adjacent conductive bars is manually controlled by means of a transformer with control of the voltage value on the voltmeter. In this case, the determination of the threshold of pain sensitivity occurs with an error due to a large, manually adjustable pitch of change in electrical voltage. In a number of experiments, it is desirable to provide a more accurate setting of the minimum values of the voltage level and the registration of the current value characterizing the minimum pain sensitivity threshold, as well as to ensure accurate repeatability of the steps of voltage level variation in different experiments with different animals. In order to exclude the possibility for animals to find equipotential bars of the cage floor to avoid electrical shock, for example, they apply electric stimulation independently to each conductive bar of the cage floor, providing a multiphase pulse repetition mode. For accurate and effective determination of the pain threshold of laboratory animals, the device MD280 was developed and implemented. Each electronic key in the device is connected to a specific register bit, and each bar of the cage floor is connected via an electronic key to a controlled constant-voltage source. In turn, the register and voltage source are connected to a control unit connected to the computer via a USB controller. In addition, the device provides correct information by eliminating the possibility of an animal avoiding electrical impact by implementing control of the pulse feed sequence with adjustable phasing (set by the time shift of the pulses on the conductive bars of the floor) and by fixing and saving the measurement sequence at each step of changing the parameters. Interaction with the device is carried out using a computer with USB 2.0 Full-Speed. Data exchange with the PC via the USB interface is performed by a USB-FIFO converter implemented on an FT245RL (FTDI) chip and a block that converts data from the FIFO buffer into internal commands and records data into the FIFO buffer from the device. The program RatCage has been developed, which provides, on the basis of the device, a study of the threshold pain sensitivity of rats. The graphical interface of the program allows at the start of work to select the parameters of the experiment: electrostimulating effects (constant, pulsed, phased, etc.), setting the values of the impact parameters (voltage amplitude, pulse duration, frequency), how parameters change (automatically or manually). After the start of the measurement signal is applied, the voltage amplitude gradually increases. The experimenter observes the behavior of the laboratory animal (rat) and when the primary nociceptive reaction (startle) appears, presses the “Remember” button. The program allows you to save these values along with the experiment protocol in the experimental database. This ensures an effective measurement of the minimum pain sensitivity threshold due to the smooth adjustment of the parameters of the electrical effect pattern (amplitude, duration, frequency of impulses, their number), automatic measurement of parameters when an animal’s primary nociceptive reaction occurs, and also the avoidance of the possibility that the animal avoids electrical impact by feeding electrical pulses with phasing. The developed approach and the implemented tools have been used in pain studies conducted at the I.P. Pavlov Institute of Physiology RAS.

Area Efficient Reconfigurable Buffer for NoC Router

In the current research, FPGA-based architecture of the Noc device reconfigurable router is suggested. Proposed router specification entry is done with the Verilog Hardware Description Language. The latest research has a five-channel router and a crossbar switch (east, west, north, south and local). Each channel has buffers and multiplexers. FIFO buffer stores data, and multiplexer monitors the input and output of data. The channel contains FIFO architecture and multiplexers. The crossbar switch is then planned and five other channels. Reducing the number of LUTs in the proposed work decreased the router area. A report is given for the number of LUTs used in a router. Results obtained indicate the area efficiency of the proposed router over existing method.

Real-time filtering on parallel SIMD architectures for automated quality inspection

Surface metrology in automated quality inspection is a field, among many others, affected by noise and thus requiring filtering. In surface metrology, filtering is required to remove undesired information from data in order to extract surface features and relevant properties necessary for quality control. Moreover, filtering requires immediate results, while the product is being manufactured. This way, quick correcting actions can be directly applied to solve possible manufacturing issues. This work proposes different strategies to filter height maps in real-time acquired using laser profilers, the most widely used inspection method in industrial applications. Different models to apply the filtering operations are considered, particularly assessing different alternatives to store previous samples in memory, which are required for data filtering. FIFO, double FIFO, circular and double circular buffers are evaluated. Furthermore, CPU parallelism, SIMD instructions and cache-line friendly data structures are analyzed. The proposed methods are extremely efficient, capable of filtering laser profiles at extremely high acquisition rates. The proposed methods are designed for real-time surface metrology, but they are very likely to find potential applications in different areas. The filters are compared in terms of accuracy and speed, including other well-known filters such as the spline filter. Tests analyze execution time, including cache efficiency and filtering accuracy. Results with synthetic data and real data obtained from steel strips show excellent performance, providing accurate results at very high speeds.

Hybrid buffers based coarse-grained power gated network on chip router microarchitecture

ABSTRACTWith the failure of Dennard’s Scaling, we cannot power on all the transistors of an circuit simultaneously for a given thermal design power. In this paper, we propose coarse-grained power gated hybrid buffer based Network on Chip router microarchitecture which a large amount of Network on Chip router power and area is consumed by the FIFO buffers. State of the art NoC router buffers is composed of SRAM, which is neither power efficient nor area efficient. We have proposed hybrid buffers based coarse-grained power gated Network on Chip router microarchitecture. As STT-MRAM (Spin Transfer Torque Magneto-resistive Random Access Memory) provides an improved solution having near zero leakage power and higher package density. Our proposed router microarchitecture improves 12.3% average packet latency as compared to state of the art power gated SRAM based router and 4.90% as compared to the fine-grained power gated hybrid buffer based router respectively for PARSEC benchmarks. We have achieved 65% and 21.34% total network energy saving for PARSEC benchmarks as compared with one without power gating and state of the art power gated SRAM based router respectively. Our hybrid router is 35.10% area efficient as compare to pure SRAM based power gated router at 32nm technology node.

On the Degree-Based Topological Indices of the Tickysim SpiNNaker Model

Tickysim is a clock tick-based simulator for the inter-chip interconnection network of the SpiNNaker architecture. Network devices such as arbiters, routers, and packet generators store, read, and write forward data through fixed-length FIFO buffers. At each clock tick, every component executes a “read” phase followed by a “write” phase. The structures of any finite graph which represents numerical quantities are known as topological indices. In this paper, we compute degree-based topological indices of the Tickysim SpiNNaker Model ( T S M ) sheet.

Multi-buffer simulations: Decidability and complexity

Multi-buffer simulation is a refinement of fair simulation between two nondeterministic Büchi automata (NBA). It is characterised by a game in which letters get pushed to and taken from FIFO buffers of bounded or unbounded capacity.Games with a single buffer approximate the PSPACE-complete language inclusion problem for NBA. With multiple buffers and a fixed mapping of letters to buffers these games approximate the undecidable inclusion problem between Mazurkiewicz trace languages.We study the decidability and complexity of multi-buffer simulations and obtain the following results: P-completeness for fixed bounded buffers, EXPTIME-completeness in case of a single unbounded buffer and high undecidability (in the analytic hierarchy) with two buffers of which at least one is unbounded. We also consider a variant in which the buffers are kept untouched or flushed and show PSPACE-completeness for the single-buffer case.

Implementation of an 8x8 Discrete Cosine Transform on Programmable System-on-chip

This paper presents experimental results that compares between a full software (SW) implementation and a software/hardware (SW/HW) co-design implementation of a DSP algorithm on a Xilinx Zynq programmable System-on-chip (SoC). The case study being used is the 8x8 two-dimensional discrete cosine transform (2D DCT), present in the popular JPEG and MPEG4-AVC encoder. The full SW design is implemented on a hardcore ARM processor on the FPGA SoC. The SW/HW co-design utilizes both the ARM processor and the Configurable Logic Blocks (CLB) of the FPGA SoC, where the communication channel is implemented using the Xillybus FIFO buffers, implemented as an external DRAM. In this case, the core 2D DCT operations are executed on the CLB, while data initialization and transfers are implemented on the processor. Results show that SW implementation is faster compared to SW/HW implementation for data inputs of less than 0.48 megapixels. As data inputs get larger, SW/HW implementation shows better performance, with up to 2x faster for 2 megapixels data input size. This study proves the viability of implementing the 2D DCT operations as dedicated hardware accelerator in multimedia encoders.

Selective Experience Replay for Lifelong Learning

Deep reinforcement learning has emerged as a powerful tool for a variety of learning tasks, however deep nets typically exhibit forgetting when learning multiple tasks in sequence. To mitigate forgetting, we propose an experience replay process that augments the standard FIFO buffer and selectively stores experiences in a long-term memory. We explore four strategies for selecting which experiences will be stored: favoring surprise, favoring reward, matching the global training distribution, and maximizing coverage of the state space. We show that distribution matching successfully prevents catastrophic forgetting, and is consistently the best approach on all domains tested. While distribution matching has better and more consistent performance, we identify one case in which coverage maximization is beneficial---when tasks that receive less trained are more important. Overall, our results show that selective experience replay, when suitable selection algorithms are employed, can prevent catastrophic forgetting.