A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock

Abstract

This brief presents a low-cost blind oversampling CDR (Clock Data Recovery) architecture that obviates the need of a dedicated clock generator or oversampling clock at the receiver end of a high-speed serial link. The proposed CDR reuses an existing at-speed clock available in the system. It deploys a sampler circuit at the input coupled to a data storage and control block that frames the serial input into a parallel output data frame along with the recovered clock. The all-digital CDR algorithm tracks clock impairments and takes appropriate action when UI (Unit Interval) boundaries are violated. Samples obtained at non-uniform time stamps near rise & fall clock edges are used to determine valid data captures. Unlike conventional oversampling CDRs, it achieves high jitter tolerance (JTOL) without storing and post processing multiple data word samples. The absence of a FIFO and elastic buffer in the design greatly reduces design size. As a result, the proposed technique achieves low power, wide-range operation with minimal hardware overhead and design implementation effort while delivering performances at par with conventional approaches. A 2Gbps CDR design in 28nm technology is demonstrated with digital area 0.00063mm2 and power 0.88mW.