Area Efficient Reconfigurable Buffer for NoC Router

Abstract

In the current research, FPGA-based architecture of the Noc device reconfigurable router is suggested. Proposed router specification entry is done with the Verilog Hardware Description Language. The latest research has a five-channel router and a crossbar switch (east, west, north, south and local). Each channel has buffers and multiplexers. FIFO buffer stores data, and multiplexer monitors the input and output of data. The channel contains FIFO architecture and multiplexers. The crossbar switch is then planned and five other channels. Reducing the number of LUTs in the proposed work decreased the router area. A report is given for the number of LUTs used in a router. Results obtained indicate the area efficiency of the proposed router over existing method.