Field Programmable Gate Array Resources Research Articles

FPGA IMPLEMENTATION OF CNN FOR DEFECT CLASSIFICATION ON CMP RING

Defect inspection is a crucial part of industrial manufacturing. However, it relies heavily on human effort on manual visual inspection. Various machine vision techniques have been introduced to replace human labour and to improve inspection quality and efficiency. The limitation of these techniques is that the algorithms need to be engineered again with each different use case. In this work, a Convolutional Neural Network (CNN) is used to classify the defects of the Chemical Mechanical Planarization (CMP) ring. The trained CNN model achieved an accuracy of 91% and the time taken for each inference process is around 1800 msec. To achieve computational efficiency, the CNN model is performed on the embedded device. The previous implementation of embedded CNN deploys OpenCL-based high-level synthesis accelerator on a high-end Field Programmable Gate Array (FPGA) board. In this work, the model inference is accelerated by PipeCNN FPGA implementation on Cyclone-VSE DE1-SoC, a low-end embedded FPGA board. Several configurations of hardware parameters are tested to search for the best setup of the FPGA resources. The hardware implementation has improved approximately seven times faster, as the inference time for each classification has improved from 1800 msec to 250 msec. However, the model implemented using the hardware is observed to produce lower inference accuracy as the accuracy drops from 91% to 81%.

Attitude stabilization of Marine Satellite Tracking Antenna using Model Predictive Control

Attitude stabilization is a necessary function for a shipboard Marine Satellite Tracking Antenna (MSTA), which is responsible for making the antenna dish track the geostationary satellite in the presence of severe environment. A control scheme based on Model Predictive Control (MPC) is proposed to stabilize the antenna dish of an MSTA, and the detailed design process from algorithm design to Hardware-in-the-loop (HIL) simulation is explained. Due to the use of stepper motor as the actuator, the MPC is proposed to deal with the speed acceleration and deceleration problems of stepper motors, which can result in the optimal velocity profile. The MPC algorithm is implemented in Field Programmable Gate Array (FPGA) with three different data types. In addition to using traditional floating-point and fixed-point data types to represent values in MPC, a special data type, half-precision floating-point, is also explored for the first time. The comparison results are presented and analyzed in terms of FPGA resource usage and algorithm execution time. The performance of the proposed control scheme is validated in HIL simulation, which is creatively implemented in a low-cost System On Chip (SOC) FPGA. The HIL simulation results demonstrate that the proposed control scheme in fixed-point MPC can satisfy the requirements of the MSTA.

A broadband MVDR beamforming core for ultrasound imaging

The Minimum Variance Distortion less Response (MVDR) beamformer is an attractive alternative to conventional delay and sum (DAS) beamformers in medical ultrasound imaging. However, it is not widely employed in medical ultrasound imaging due to its computational complexity. In this paper, we intend to present a novel broadband MVDR beamformer architecture and its implementation for up to 32 channel ultrasound imaging system. The proposed architecture is based on the subarray MVDR and Dichotomous Coordinate Descent (DCD) iteration based adaptive weight computation. A Field Programmable Gate Array (FPGA) based ultrasound system prototype set up is designed, and the proposed MVDR beamforming Core is emulated on the FPGA. The proposed beamforming core could achieve up to 65.5 fps for a 640 x 480 ultrasound frame. The ultrasound system prototype operates at 20 MHz sampling frequency, and the FPGA implementation resulted in approximately 35% of FPGA resources (Xilinx Kintex-7 410T). Image quality comparisons in terms of Contrast Ration (CR) and Contrast to Noise Ratio (CNR) were performed with MATLAB™ MVDR model ported on the Verasonics™ Vantage-64 ultrasound research platform.

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge. In this paper, a novel design approach is proposed for the FPGA-implementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2μsec with 30% to 50% fewer resources as compared to existing techniques.

Nanosecond machine learning event classification with boosted decision trees in FPGA for high energy physics

We present a novel implementation of classification using the machine learning/artificial intelligence method called boosted decision trees (BDT) on field programmable gate arrays (FPGA). The firmware implementation of binary classification requiring 100 training trees with a maximum depth of 4 using four input variables gives a latency value of about 10 ns, independent of the clock speed from 100 to 320 MHz in our setup. The low timing values are achieved by restructuring the BDT layout and reconfiguring its parameters. The FPGA resource utilization is also kept low at a range from 0.01% to 0.2% in our setup. A software package called achieves this implementation. Our intended user is an expert in custom electronics-based trigger systems in high energy physics experiments or anyone that needs decisions at the lowest latency values for real-time event classification. Two problems from high energy physics are considered, in the separation of electrons vs. photons and in the selection of vector boson fusion-produced Higgs bosons vs. the rejection of the multijet processes.

Design of High Speed and Low Area Confined Multiplier on FPGA

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

CoAP Acceleration on FPSoC for Resource Constrained Internet of Things Devices

Data communication stack on Internet of Things (IoT)-devices is traditionally implemented in software as a part of their operating systems. In IoT-applications for which resource constrained IoT-devices are deployed, leveraging microprocessor(s) for both computing and data communication tasks may result in poor application performance and high power consumption. In order to alleviate these performance and power issues, using System on Chip (SoC) field programmable gate arrays (FPGAs) for the hardware acceleration of the performance- or power-critical software tasks is a recent, popular trend in the literature. On the other hand, constrained application protocol (CoAP) is a pivotal network protocol for many IoT-applications. Motivated by these facts, in this article, a hardware accelerator for a CoAP server network stack is proposed and realized on a SmartFusion2 SoC FPGA. The hardware accelerated CoAP server network stack is thoroughly evaluated and compared in terms of its performance, latency, power consumption, and FPGA resource utilization against a baseline software implemented CoAP server network stack. The evaluation results obtained clearly show that the CoAP hardware accelerator provides significantly higher performance and lower response message latency, while consuming significantly less power. Consequently, the CoAP hardware accelerator proposed seems to be a strong viable solution for the resource constrained IoT-devices.

Efficient FPGA-Based Real-Time Implementation of Model Predictive Control for Single-Phase Direct Matrix Converter

Finite control set model predictive control (FCS-MPC) is an optimal control strategy that solves user-defined objective functions to determine the best control action for the next time interval. Real-time implementations of model predictive control techniques are quite challenging for certain topologies due to computation complexities. In this paper, key aspects of achieving robust, reliable, and efficient field programmable gate arrays (FPGAs) based model predictive control are presented for single-phase direct matrix topology. The effectiveness of FPGA-based model predictive control is validated experimentally using an ALTERA Cyclone IV FPGA. Experimental results show that an effective load current control performance is obtained by taking advantage of pipelining capability of the FPGA device. The tradeoff between control bandwidth, FPGA resources, and hardware utilization is discussed.

Algorithmic TCAM on FPGA with data collision approach

<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>

New First-Order Secure AES Performance Records

Being based on a sound theoretical basis, masking schemes are commonly applied to protect cryptographic implementations against Side-Channel Analysis (SCA) attacks. Constructing SCA-protected AES, as the most widely deployed block cipher, has been naturally the focus of several research projects, with a direct application in industry. The majority of SCA-secure AES implementations introduced to the community opted for low area and latency overheads considering Application-Specific Integrated Circuit (ASIC) platforms. Albeit a few, those which particularly targeted Field Programmable Gate Arrays (FPGAs) as the implementation platform yield either a low throughput or a not-highly secure design.In this work, we fill this gap by introducing first-order glitch-extended probing secure masked AES implementations highly optimized for FPGAs, which support both encryption and decryption. Compared to the state of the art, our designs efficiently map the critical non-linear parts of the masked S-box into the built-in Block RAMs (BRAMs).The most performant variant of our constructions accomplishes five first-order secure AES encryptions/decryptions simultaneously in 50 clock cycles. Compared to the equivalent state-of-the-art designs, this leads to at least 70% reduction in utilization of FPGA resources (slices) at the cost of occupying BRAMs. Last but not least, we provide a wide range of such secure and efficient implementations supporting a large set of applications, ranging from low-area to high-throughput.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

SummaryStatistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA.

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

A hybrid hardware oriented motion estimation algorithm for HEVC/H.265

High Efficiency Video Coding (HEVC) is the latest video coding standard that supports high resolution videos by providing approximately twice the compression efficiency as compared to its previous standard H.264. Motion Estimation (ME) in HEVC is the most computation-intensive block as a result it becomes a bottleneck in the design of the encoder while implementing video applications on various computing platforms such as general purpose and embedded processors. So developing computational efficient architectures on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platforms is inevitable. This paper proposes a fast hybrid search pattern algorithm and its hardware architecture for encoding UHD videos. The proposed Integer ME (IME) algorithm requires an average of 11.19% less encoding time than the default Test Zone Search (TZS) algorithm in HM reference software with compromising decrement in PSNR and increment in bit rate. The proposed architecture is implemented in both FPGA and ASIC platform with TSMC 90 nm technology library. It consumed 32-33% of resources in Virtex-7 FPGA and 2784.4 K equivalent gate count (in terms of NAND ) and 18 kB of memory, respectively. The results show that maximum frequency of the proposed architecture is 162 MHz and a total power consumption is 463.4 mW. The architecture provides a maximum throughput of 2.78 Gpixels/sec due to it process $$32\times 32$$ CU comparatively much less clock cycles (59.5) as compared to the state-of-the-art literature . Further, it supports 8K UHD $$(8192\times 4320)$$ @ 78 fps.

Hardware Architecture Proposal for TEDA Algorithm to Data Streaming Anomaly Detection

The amount of data in real-time, such as time series and streaming data, available today continues to grow. Being able to analyze this data the moment it arrives can bring an immense added value. However, it also requires a lot of computational effort and new acceleration techniques. As a possible solution to this problem, this paper proposes a hardware architecture for Typicality and Eccentricity Data Analytic (TEDA) algorithm implemented on Field Programmable Gate Arrays (FPGA) for use in data streaming anomaly detection. TEDA is based on a new approach to outlier detection in the data stream context. The suggested design has a full parallel input of N elements and a 3-stage pipelined architecture to reduce the critical path and thus optimize the throughput. In order to validate the proposals, results of the occupation and throughput of the proposed hardware are presented. The design reached a speed of up to 693x, compared to other software platforms, with a throughput of up to 10.96 MSPs (Mega Sample Per second), using a small portion of the target FPGA resources. Besides, the bit accurate simulation results are also presented. This work is a pioneer in the hardware implementation of the TEDA technique in FPGA. The project aims to Xilinx Virtex-6 xc6vlx240t-1ff1156 as the target FPGA.

Characteristics and comparison of two digital quasi-Gauss filters for gamma spectroscopy

This paper presents two digital quasi-Gauss filters, the first of which is a digital CR-RCm filter with the function of pole-zero cancellation (digital CRPZC-RCm filter) and the second a digital Sallen-Key filter (digital S-K filter). The digital filters are established according to the differential equations of an analog CRPZC-RCm circuit and an analog S-K circuit, respectively. Characteristics including frequency response, noise suppression and stability for both digital filters are discussed and improved algorithm cascade structures are obtained to reduce the resources consumption of field programmable gate arrays (FPGAs). To compare the two digital filters, the energy resolution (@Cs-137, 662 keV) for LaBr3(Ce) and NaI(Tl) detectors is calculated for the digital spectroscopy system and the analog spectroscopy system from CANBERRA. The results prove that the two digital filters exhibit similar performance in frequency response, noise suppression and energy resolution improvement. Further, the optimum energy resolution (@Cs-137, 662 keV) for both digital filters is slightly superior to that of CANBERRA. The digital S-K filter consumes fewer FPGA resources compared to the digital CRPZC-RCm filter due to its simpler algorithm cascade structure, though the digital S-K filter becomes unstable when its gain (K) exceeds a certain threshold.

Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml

We present the implementation of binary and ternary neural networks in the hls4ml library, designed to automatically convert deep neural network models to digital circuits with field-programmable gate arrays (FPGA) firmware. Starting from benchmark models trained with floating point precision, we investigate different strategies to reduce the network’s resource consumption by reducing the numerical precision of the network parameters to binary or ternary. We discuss the trade-off between model accuracy and resource consumption. In addition, we show how to balance between latency and accuracy by retaining full precision on a selected subset of network components. As an example, we consider two multiclass classification tasks: handwritten digit recognition with the MNIST data set and jet identification with simulated proton-proton collisions at the CERN Large Hadron Collider. The binary and ternary implementation has similar performance to the higher precision implementation while using drastically fewer FPGA resources.

Modification and hardware implementation of cortex‐like object recognition model

Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.

Emulator of a Boost Converter for Educational Purposes

Project-based learning (PBL) is proposed for the development of a Hardware-in-the-Loop (HIL) platform and the design of its digital controller for an undergraduate course on Digital Electronic Systems. The objective for students is the design of a digitally controlled HIL Boost converter, a digital pulse-width modulator (DPWM) and a current mode controller, implemented in field-programmable gate array (FPGA) devices. To this end, the different parts of the project are developed and evaluated, maximizing the use of FPGA resources in the design of the HIL and DPWM blocks, and applying design techniques that minimize the use of the digital resources used in the design of the controller. Students are equipped with a new individualized educational experience, allowing them to test their technical competence and knowledge in an environment close to the reality of the industry.

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS.

Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores

Partially reconfigurable designs on field-programmable gate array (FPGA) bring an opportunity for developers to license third-party intellectual property (IP) cores. There are multiple IP licensing models that can be used by the FPGA IP market. Their focus is mainly on feasibility and security; however, two major challenges have been ignored by almost all of them. First, both academic or industrial tools do not provide a flow to generate IPs in a standalone environment. Second, these tools only offer manual floorplanning of the IPs, which is both time and performance inefficient. In this work, we present a framework, that can be used by multiple parties to generate different parts of a design independently, that are compatible with each other. It also provides automatic floorplanning based on mixed-integer linear programming (MILP) that considers the distribution of heterogeneous resources in modern FPGAs, with efficient resource utilization as the main objective. The proposed floorplanning is evaluated with benchmarks from the related work. Furthermore, a use case of internal and open-source designs is used for the validation and evaluation of the independent IP generation and the floorplanner.