Field Programmable Gate Array Board Research Articles

Development process of FPGA based technology for control rod drive systems of experimental power reactor

The Experimental Power Reactor (EPR) design was developed in Indonesia based on HTGR technology and employed fully-digitized system for reactor instrumentation and control. The field programmable gate array (FPGA) technology which has advantages in minimizing a common cause failure and vulnerability from the cyber- attack was employed in the design of control rod drive system (CRDS) of EPR. This paper discusses the process in developing of FPGA-based CRDS for EPR using the V-Model approach. Verification and adjustment were conducted toward the CRDS design requirement established in the preliminary research based on relevant design criteria, standard, and most recent data. The rule checking method has been used to verify that specified rules and criterias have been adhered. In this study a simulation prototype was designed and implemented into Digilent Basys3 FPGA board in order to conduct a thorough design verification and validation process. The results showed the conformity of system requirements with the corresponding standard and design criteria. In addition, the use of simulation prototypes will be beneficial for verification process and tends to increase the effectiveness of V-model in the development of control system for CRDS. The approach used in this study can be applied to designing other FPGA-based systems of EPR.

Edge of Medical Things Implementation for Deep Learning-Based Cognitive Task Recognition

The emergence of edge devices for the Internet of Medical Things (IoMT) has enabled the integration of low-power resource-limited hardware units with communication technologies for smart healthcare applications including, brain-computer interface (BCI) and mental health management. Implementation of BCI systems on edge devices can provide high clinical decision accuracy with low latency and power consumption while reducing cloud-based training and communication. Hence, this article presents the edge of medical things (EoMT) implementation for cognitive task recognition (CTR) from electroencephalogram (EEG) signals in portable BCI systems. The proposed implementation exploits deep learning-based CTR on different computing platforms for edge devices including Arduino Due and Portenta H7 micro-controllers, Intel Movidius Neural Compute Stick 2 (NCS2), and Mimas v2 Spartan 6 field-programmable gate array (FPGA) board, along with IoMT communication technologies toward transmission of CTR information to caregivers. The real-time CTR performance results on different public and self-recorded databases indicate that the EoMT implementation scheme achieves high accuracies of 99.30 percent and 99.02 percent for public databases, and 96 percent and 89.50 percent for self-recorded databases, with low power consumption and latency, which makes it suitable for the IoMT context.

An Optimization on the Neuronal Networks Based on the ADEX Biological Model in Terms of LUT-State Behaviors: Digital Design and Realization on FPGA Platforms.

Simple SummaryThe brain is an incredibly complex system possessing outstanding abilities to perform difficult tasks through a vast number of densely interconnected neurons. Aimed at discovering the underlying mechanisms of the brain, a number of spiking neural networks have been proposed to mimic biological neural dynamics. Subsequently, to perceive how the neural networks in the brain work, simulation and hardware realization of large-scale systems, similar to the brain, is an essential requirement. Behavior of a single neuron can be described by the mathematical equations in different levels of computing and biological accuracy. In this approach, a new modified ADEX model is presented based on sampling frequency by the nonlinear functions of the original model. This new model is capable for reproducing all aspects of the original model in low-error and high-degree of similarity conditions. Finally, the proposed model can be implemented on digital hardware platforms to have a real digital system. Digital results show the increase in system speed (frequency) and overall saving in hardware resources (compared by the original model and other similar works). This low-cost digital hardware is applied in large-scale neuronal networks.Design and implementation of biological neural networks is a vital research field in the neuromorphic engineering. This paper presents LUT-based modeling of the Adaptive Exponential integrate-and-fire (ADEX) model using Nyquist frequency method. In this approach, a continuous term is converted to a discrete term by sampling factor. This new modeling is called N-LUT-ADEX (Nyquist-Look Up Table-ADEX) and is based on accurate sampling of the original ADEX model. Since in this modeling, the high-accuracy matching is achieved, it can exactly reproduce the spiking patterns, which have the same behaviors of the original neuron model. To confirm the N-LUT-ADEX neuron, the proposed model is realized on Virtex-II Field-Programmable Gate Array (FPGA) board for validating the final hardware. Hardware implementation results show the high degree of similarity between the proposed and original models. Furthermore, low-cost and high-speed attributes of our proposed neuron model will be validated. Indeed, the proposed model is capable of reproducing the spiking patterns in terms of low overhead costs and higher frequencies in comparison with the original one. The properties of the proposed model cause can make it a suitable choice for neuromorphic network implementations with reduced-cost attributes.

Eğitsel SDR Tekniklerine Dayalı FPGA Tabanlı FM Radyo Verici Tasarım ve Uygulaması

The basic purpose of Software Defined Radio (SDR) systems is to use a digital signal processor to numerically handle radio signals. The use of a processor like a Field Programmable Gate Array (FPGA) to perform tasks like modulation, demodulation, signal creation, and line coding on these systems dramatically decreases the demand for analog circuit-based hardware. FPGAs are digital integrated circuits with a wide range of applications which are made up of links between programmable logic blocks. It's aimed at assisting the creator realize the logic functions that the designer needs. In consequence, the user may change the function of each logic block. VHSIC Hardware Description Language (VHDL) is commonly used in FPGA programming. In this study, VHDL code was created, and a FM transmitter was implemented on a FPGA board (CMOD A7) in this research. The sound card interface on the PC used to send and receive the signals while suitable ADC and DAC cards are used on the FPGA side for the same purpose. Audacity program was used to playback the sample wav files while HDSDR SDR program was used to monitor and record the signals in wav file format. Finally, using the MATLAB code, the recorded transmitter signal was demodulated offline, and the output was stored to the hard drive. The demodulated signal obtained is identical to the initial modulation signal, indicating that the modulation was correctly executed. As a result, a perfect foundation for the development and training of SDR systems using FPGA has been established.

A Novel Processor for Artificial Intelligence Acceleration

A variable predicate logic processor (VPLP) is proposed for artificial intelligence (AI), robotics, computer-aided medicine, electronic security, and other applications. The development is realized as an accelerating unit in AI computing machines. The difference from known designs, the datapath of this processor consists of universal gates changing on-the-fly their logical styles-subsets of predicate logic according to the data type and implemented instructions. In this paper, the processor’s reconfigurable gates and the main units are proposed, designed, modeled, and verified using a Field-Programmable Gate Array (FPGA) board and corresponding computer-aided design (CAD) tool. The implemented processor confirmed its reconfigurability on-the-fly performing testing codes. This processor is interesting in accelerating AI computing, molecular and quantum calculations in science, cryptography, computer-aided medicine, robotics, etc.

Field Programmable Gate Array Based Torque Predictive Control for Permanent Magnet Servo Motors.

With the increasing demand for legged robots, the importance of the joint drive is increasing. The dynamic performance of the inner-most torque/current control loop conditions the capabilities of the whole joint system. In this paper, a direct torque control based on a prediction model is proposed. The motor torque is estimated by considering calculation and measurement delay; error estimation and torque tracking error are observed and compensated. The control algorithm was implemented on a Field Programmable Gate Array (FPGA) board to apply the capabilities of concurrency calculation of the FPGA. The effectiveness of the proposed control algorithm was experimentally verified. Compared with the commonly used Field Oriented Control (FOC) current controller, the presented controller can not only improve the dynamic performance of the motor but also reduce the average switching times of the inverter.

Using machine learning for anomaly detection on a system-on-chip under gamma radiation

The emergence of new nanoscale technologies has imposed significant challenges to designing reliable electronic systems in radiation environments. A few types of radiation like Total Ionizing Dose (TID) can cause permanent damages on such nanoscale electronic devices, and current state-of-the-art technologies to tackle TID make use of expensive radiation-hardened devices. This paper focuses on a novel and different approach: using machine learning algorithms on consumer electronic level Field Programmable Gate Arrays (FPGAs) to tackle TID effects and monitor them to replace before they stop working. This condition has a research challenge to anticipate when the board results in a total failure due to TID effects. We observed internal measurements of FPGA boards under gamma radiation and used three different anomaly detection machine learning (ML) algorithms to detect anomalies in the sensor measurements in a gamma-radiated environment. The statistical results show a highly significant relationship between the gamma radiation exposure levels and the board measurements. Moreover, our anomaly detection results have shown that a One-Class SVM with Radial Basis Function Kernel has an average recall score of 0.95. Also, all anomalies can be detected before the boards are entirely inoperative, i.e. voltages drop to zero and confirmed with a sanity check.

An Efficient YOLO Algorithm with an Attention Mechanism for Vision-Based Defect Inspection Deployed on FPGA.

Industry 4.0 features intelligent manufacturing. Among them, the vision-based defect inspection algorithm is remarkable for quality control in parts manufacturing. With the help of AI and machine learning, auto-adaptive instead of manual operation is achievable in this field, and much progress has been made in recent years. In this study, considering the demand of inspection features in industrialization, we made further improvement in smart defect inspection. An efficient algorithm using Field Programmable Gate Array (FPGA)-accelerated You Only Look Once (YOLO) v3 based on an attention mechanism is proposed. First, because of the relatively fixed camera angle and defect features, an attention mechanism based on the concept of directing the focus of defect inspection is proposed. The attention mechanism consists of three improvements: (a) image preprocessing, which is to tailor images for selectively concentrating on the defect relevant things. Image preprocessing mainly includes cutting, zooming and splicing, named CZS operations. (b) Tailoring the YOLOv3 backbone network, which is to ignore invalid inspection regions in deep neural networks and optimize the network structure. (c) Data augmentation. First, two improvements can be made to efficiently reduce deep learning operations and accelerate the inspection speed, but the preprocessed images are similar and the lack of diversity will reduce network accuracy. So, (c) is added to mitigate the lack of considerable amounts of training data. Second, the algorithm is deployed on a PYNQ-Z2 FPGA board to meet the industrialization production requirements for accuracy, efficiency and extensibility. FPGA can provide a low-latency, low-cost, high-power-efficiency and flexible architecture that enables deep learning acceleration for industrial scenarios. A Xilinx Deep Neural Network Development Kit (DNNDK) converted the improved YOLOv3 to Programmable Logic (PL), which can be deployed on FPGA. The conversion process mainly consists of pruning, quantization and compilation. Experimental results showed that the algorithm had high efficiency, inspection accuracy reached 99.2%, processing speed reached 1.54 Frames per Second (FPS), and power consumption was only 10 W.

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis

Field programmable gate arrays (FPGAs) have become widely prevalent in recent years as a great alternative to application-specific integrated circuits (ASIC) and as a potentially cheap alternative to expensive graphics processing units (GPUs). Introduced as a prototyping solution for ASIC, FPGAs are now widely popular in applications such as artificial intelligence (AI) and machine learning (ML) models that require processing data rapidly. As a relatively low-cost option to GPUs, FPGAs have the advantage of being reprogrammed to be used in almost any data-driven application. In this work, we propose an easily scalable and cost-effective cluster-based co-processing system using FPGAs for ML and AI applications that is easily reconfigured to the requirements of each user application. The aim is to introduce a clustering system of FPGA boards to improve the efficiency of the training component of machine learning algorithms. Our proposed configuration provides an opportunity to utilise relatively inexpensive FPGA development boards to produce a cluster without expert knowledge in VHDL, Verilog, or the system designs related to FPGA development. Consisting of two parts – a computer-based host application to control the cluster and an FPGA cluster connected through a high-speed Ethernet switch, allows the users to customise and adapt the system without much effort. The methods proposed in this paper provide the ability to utilise any FPGA board with an Ethernet port to be used as a part of the cluster and unboundedly scaled. To demonstrate the effectiveness of the proposed work, a two-part experiment to demonstrate the flexibility and portability of the proposed work – a homogeneous and heterogeneous cluster, was conducted with results compared against a desktop computer and combinations of FPGAs in two clusters. Data sets ranging from 60,000 to 14 million, including stroke prediction and covid-19, were used in conducting the experiments. Results suggest that the proposed system in this work performs close to 70% faster than a traditional computer with similar accuracy rates.

Review and design of modular multilevel inverter with modified multicarrier PWM techniques for solar PV applications

PurposeThese implementations not only generate excessive voltage levels to enhance the quality of power but also include a detailed investigating of the various modulation methods and control schemes for multilevel inverter (MLI) topologies. Reduced harmonic modulation technology is used to produce 11-level output voltage with the production of renewable energy applications. The simulation is done in the MATLAB/Simulink for 11-level symmetric MLI and is correlated with the conventional inverter design.Design/methodology/approachThis paper is focused on investigating the different types of asymmetric, symmetric and hybrid topologies and control methods used for the modular multilevel inverter (MMI) operation. Classical MLI configurations are affected by performance issues such as poor power quality, uneconomic structure and low efficiency.FindingsThe variations in both carrier and reference signals and their performance are analyzed for the proposed inverter topologies. The simulation result compares unipolar and bipolar pulse-width modulation (PWM) techniques with total harmonic distortion (THD) results. The solar-fed 11-level MMI is controlled using various modulation strategies, which are connected to marine emergency lighting loads. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by using SPARTAN 3A field programmable gate array (FPGA) board and the least harmonics are obtained by improving the power quality.Originality/valueThe simulation result compares unipolar and bipolar PWM techniques with THD results. Various modulation techniques are used to control the solar-fed 11-level MMI, which is connected to marine emergency lighting loads. The entire hardware system is controlled by a SPARTAN 3A field programmable gate array (FPGA) board, and the power quality is improved to achieve the lowest harmonics possible.

Dynamic centralized control and intelligent load management system of a remote residential building with V2H technology

Energy is the main engine and the active element for all growth and development. It is the basic element for all sectors of the economy and a companion to human life. It is also not forgotten that most of the energy used in the whole world is traditional and unsustainable energy, as well as polluting the environment and causing harmful emissions. Sustainable is based primarily on environmental protection. Massive population growth is accompanied by a significant increase in energy consumption. Currently, most countries are turning to rely mainly on renewable energy sources. To achieve the maximum benefit from the energy, the tendency is to manage energy within the home to avoid the occurrence of energy losses. In this paper, an efficient home energy management system (HEMS) is proposed. This system is based on the use of a field-programmable gate array (FPGA) for home energy management. The proposed HEMS takes into account both generation and consumption as FPGA manages the feeding process through the sources. The prototype is implemented using Altera Cyclone IV EP4CE6 FPGA board using QUARTUS II software. The home is fed through PV, wind and fuel cells (FC) sources. If there is a shortage in energy production and the three sources are unable to cover the loads, the batteries enter into service to cover this shortage. If the sources and batteries are unable to cover the required loads, the EV contributes to covering the load, but with specific constraints set by the owner. The proposed HEMS works to control the feeding of the loads, as it schedules the feeding of the loads according to priority in the event of severe energy shortages and the inability of the sources, batteries and the EV to cover the loads. The experimental and simulation results proved the ability of the proposed system to respond to the demand by managing high energy-consuming household appliances according to the pre-set priority.

A low resource consumption Arbiter PUF improved switch component design for FPGA

Aiming at the problems of poor uniqueness and high resource consumption of slice after the implementation of Arbiter physical unclonable function (Arbiter PUF) on field programmable gate array (FPGA), a new improved scheme of switch component structure is proposed. The switch component structure of the improved scheme adopts the parallel-connected mode to improve the uniqueness of the circuit, which avoids the cross-connected mode unable to achieve symmetrical layout on FPGA. At the same time, the improved scheme uses lookup tables to construct the structure of programmable delay line (PDL) with a multiplexer (MUX), which can reduce the internal resource consumption of slice while receiving the same 64-bit challenges. The improved scheme was tested on FPGA boards, the uniqueness and steadiness of different switch component schemes are compared and analyzed, and the feasibility of the improved scheme is verified. The results show that in the generation of Arbiter PUF, compared with the conventional scheme, the improved scheme reduces the resource consumption and improves the uniqueness by 22.2%; Compared with the MUX + MUX scheme, the improved scheme saves 50% of resource consumption while maintaining good uniqueness.

Stochastic Computing Using Amplitude and Frequency Encoding

Stochastic computing (SC) is a type of logic computation based on stochastic bit stream instead of the binary numbers (BNs). It is pseudo-analog computation in the digital domain that can realize multiplication, addition, and complex function computations. In this brief, a new encoding method, referred to as amplitude and frequency encoding (AFE) for SC, is presented. It extends SC to use multibit streams instead of bit streams to represent data. This method still uses the expectation of streams to achieve computation. Compared with the conventional stochastic bit stream, AFE realizes low-latency and low-area occupation than the conventional SC method. The rationality of the circuits is also examined from a mathematical perspective. The hardware logic circuit of AFE SC, including the multiplier, adder, and converter, was designed and implemented by a field-programmable gate array (FPGA). In addition, the latency of the computing, area, and precision of AFE SC was measured based on the FPGA board.

Design and Implementation of UART Using FPGA Board

Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receiver, Transmitter, Microprogrammed Controller and Field Programmable Gate Array (FPGA).

Smart centralized energy management system for autonomous microgrid using FPGA

Smart energy management system (SEMS) has become an effective energy-saving tool. In this paper, an efficient energy management system is used for a hybrid system consists of PV, Fuel Cells (FCs), and wind energy systems. The hybrid system is accompanied by a battery energy storage system to act as a backup source in case that the loads exceed the power produced from the three sources. The SEMS is implemented on Altera Cyclone IV EP4CE6 field-programmable gate arrays (FPGA) board using QUARTUS II software and LABVIEW. FPGAs are highly flexible and reprogrammable logic devices. Analog to digital converter (ADC) is used to interface the current and voltage of the three sources with FPGA. As a result of the weather fluctuations, the voltage of the three sources is not stable. Therefore, the voltage of the three sources is adjusted using the Buck-Boost converter technology, which is set at 24 V until the merging process takes place. The results prove the high efficiency of the FPGA and its high response to the load changes.

Secure lightweight obfuscated delay-based physical unclonable function design on FPGA

The internet of things (IoT) describes the network of physical objects equipped with sensors and other technologies to exchange data with other devices over the Internet. Due to its inherent flexibility, field-programmable gate array (FPGA) has become a viable platform for IoT development. However, various security threats such as FPGA bitstream cloning and intellectual property (IP) piracy have become a major concern for this device. Physical unclonable function (PUF) is a promising hardware fingerprinting technology to solve the above problems. Several PUFs have been proposed, including the implementation of reconfigurable-XOR PUF (R-XOR PUF) and multi-PUF (MPUF) on the FPGA. However, these proposed PUFs have drawbacks, such as high delay imbalances caused by routing constraints. Therefore, in this study, we explore relative placement method to implement the symmetric routing in the obfuscated delay-based PUF on the FPGA board. The delay analysis result proves that our method to implement the symmetric routing was successful. Therefore, our work has achieved good PUF quality with uniqueness of 48.75%, reliability of 99.99%, and uniformity of 52.5%. Moreover, by using the obfuscation method, which is an Arbiter-PUF combined with a random challenge permutation technique, we reduced the vulnerability of Arbiter-PUF against machine learning attacks to 44.50%.

Invention of a fast response biosensor based on Au-PolyPyrrole nanocomposite-modified quartz crystal to detect morphine concentration

A biosensor based on a 20 MHz oscillator was designed by modifying the quartz surface with the Au nanoparticle in PolyPyrrole (AuNP-PPy) layer. In this design, a new field programmable gate array board was used. The AuNP-PPy composite was layered on a quartz surface with 5 μm thick using centrifugal force as simple method. Biosensor components were characterized by FESEM, XRD and FTIR spectrum. The recording of the frequency of the biosensors before the detection of morphine showed that the syntheses were the same, the frequency of all the sensors were almost equal and the experiments were repeatable. The biosensor was stable up to 50 °C but performed better at 28 °C. The limit of morphine concentration detection by biosensor was 0.1 ngml-1. Detection of morphine concentration in unknown samples showed a detection error of less than 4%. Regeneration results showed that this biosensor can be used up to 8 times in a row.

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.

Field-programmable gate array (FPGA) based programmable digital emulator of vibratory microelectromechanical systems (MEMS) gyroscopes.

This paper presents a hardware emulator of microelectromechanical systems (MEMS) vibratory gyroscopes that can be used for characterization and verification of control/interface electronics by means of hardware-in-the-loop testing, thus speeding up design cycles by decoupling these tasks from the often longer MEMS design and fabrication cycles. The easily re-configurable hardware emulator is completely synthesized on a field-programmable gate array board. The emulator is shown to successfully model the Coriolis effect along with the prominent error sources present in typical MEMS gyroscopes, namely, quadrature error, spring nonlinearity, and thermo-mechanical, electronic, and environmental noise. Preliminary experimental results characterizing the noise and nonlinearity models based on a prototype with user-controllable device parameters synthesized on the Xilinx Zynq®-7020 SoC (Digilent ZYBO Z7 board) are presented.

Real-Time FPGA/CPU-Based Simulation of a Full-Electric Vehicle Integrated with a High-Fidelity Electric Drive Model

Real-time simulations refer to the simulations of a physical system where model equations for one time-step are solved within the same time period as in reality. An FPGA/CPU-based real-time simulation platform is presented in this paper, with a full-electric vehicle model implemented in a central processing unit (CPU) board and an electric drive model implemented in a field programmable gate arrays (FPGA) board. It has been a challenge to interface two models solved with two different processors. In this paper, one open-loop and three closed-loop interfaces are proposed. Real-time simulation results show that the best method is to transmit electric machine speed from the vehicle model to the electric derive model, with feedback electric machine torque calculated in FPGA. In addition, a virtual vehicle testing tool (CarMaker) is used when building the vehicle model, achieving more accurate modeling of vehicle subsystems. The presented platform can be used to verify advanced vehicle control functions during hardware-in-the-loop (HIL) testing. Vehicle anti-slip control is used as an example here. Finally, experiments were performed by connecting the real-time platform with a back-to-back electric machine test bench. Results of torque, rotor speed, and d&q axis currents are all in good agreement between simulations and experiments.