A low resource consumption Arbiter PUF improved switch component design for FPGA

Abstract

Aiming at the problems of poor uniqueness and high resource consumption of slice after the implementation of Arbiter physical unclonable function (Arbiter PUF) on field programmable gate array (FPGA), a new improved scheme of switch component structure is proposed. The switch component structure of the improved scheme adopts the parallel-connected mode to improve the uniqueness of the circuit, which avoids the cross-connected mode unable to achieve symmetrical layout on FPGA. At the same time, the improved scheme uses lookup tables to construct the structure of programmable delay line (PDL) with a multiplexer (MUX), which can reduce the internal resource consumption of slice while receiving the same 64-bit challenges. The improved scheme was tested on FPGA boards, the uniqueness and steadiness of different switch component schemes are compared and analyzed, and the feasibility of the improved scheme is verified. The results show that in the generation of Arbiter PUF, compared with the conventional scheme, the improved scheme reduces the resource consumption and improves the uniqueness by 22.2%; Compared with the MUX + MUX scheme, the improved scheme saves 50% of resource consumption while maintaining good uniqueness.