Field Plate Length Research Articles

Low turn-on voltage AlGaN/GaN Schottky barrier diode with a low work function anode and high work function field plate

AlGaN/GaN Schottky barrier diodes (SBDs) with a low work function W anode and a high work function Ni field plate on sapphire substrates are investigated in this Letter. The low work function metal W leads to the low turn-on voltage, while the high work function metal Ni maintains the leakage current and increases the breakdown voltage. An ultralow turn-on voltage of 0.23 V determined by the positive fixed charge at the AlGaN/Si3N4 interface is achieved in this W/Ni SBD. More importantly, benefitting from the dual-metal anode/field plate structure, the on-resistance decreases from 7.99 to 5.53 Ω mm, and the breakdown voltage increases from 493 to 1219 V. In addition, the turn-on voltage decreases less than 57%, and the on-resistance increases less than 186% at a high temperature up to 120 °C. The W/Ni SBD with a cathode–anode length of 18 μm and a field plate length of 4 μm shows a low turn-on voltage of 0.23 V, a low on-resistance of 5.53 Ω mm, a leakage current of 0.65 mA/mm, and a high breakdown voltage of 1.21 kV, indicating a great potential for power electronic applications.

Dynamic RON Degradation Suppression by Gate Field Plate in Partially Recessed AlGaN/GaN Metal–Insulator–Semiconductor High‐Electron‐Mobility Transistors

This study investigates the impact of gate field plate (G‐FP) lengths on the dynamic on‐resistance degradation in partially recessed‐gate D‐mode GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MIS‐HEMTs). Devices with G‐FPs of varying lengths are fabricated, and their electrical characteristics are evaluated. It is found that G‐FPs effectively reduce electron trapping and suppress the dynamic on‐resistance degradation, leading to improved device performance. The study provides design suggestions for enhancing the reliability and stability of AlGaN/GaN‐based MIS‐HEMTs.

Field Plate Integration for Mitigating Partial Discharge Activity in PCB-Embedded Power Electronic Modules

This paper proposes a concept based on field plate (FP) integration inside printed circuit board (PCB)-embedded power modules. The goal is to reduce the electric field at their surface and thus increase the partial discharge inception voltage (PDIV). Electrostatic simulations are first carried out to analyze the electric field reduction induced by the use of FPs. Then, dedicated experiments are proposed to demonstrate that the actual PDIV increases in AC sinus 50 Hz when FPs are implemented. More specifically, it is observed that an optimal FP length exists. Several analyses based on simulations and experiments are thus proposed to explain this phenomenon. Finally, an assessment of PD activity and PD location is presented to support the analysis. AC sinus 50 Hz characterizations indicate that PDIV can be increased by 178% compared to PCBs without FPs with a proper definition of equipotential prolongation and PCB length.

Scaling of E-mode power GaN-HEMTs for low voltage/low Ron applications: Implications on robustness

We analyze the impact of scaling on the off-state, three-terminal, lateral breakdown of 100 V E-mode p-GaN/AlGaN/GaN HEMTs for low-voltage/low on-resistance applications. To this aim, we compared device structures with different SiO2 dielectric thickness below the field plate, and varying gate-to-drain spacing and field-plate dimensions. The results indicate that: a) the breakdown voltage depends on the geometry and on the thickness of the dielectric under the field plate (tSiO2); b) scaling the dielectric thickness increases the sensitivity of breakdown voltage to the gate-drain distance, while preserving device robustness (breakdown voltages above 150 V for a 100 V technology); c) for the devices with thinner dielectric, breakdown voltage scales linearly with gate drain distance, and with field plate length. A further analysis of the data reveals that the critical parameter in terms of reliability is the distance between the field-plate edge and the drain contact; d) scaling of the dielectric thickness does not enhance charge trapping phenomena. In summary, the results provide guidelines for scaling GaN HEMT device dimensions, while preserving reliability and immunity to charge trapping phenomena.

Physical insights into the reliability of sunken source connected field plate GaN HEMTs for mm-wave applications

This article investigates the incorporation of field plates in AlGaN/GaN High Electron Mobility Transistors (HEMTs) which leading to enhancement in the device breakdown voltage and a reduction in the reverse leakage current. Using Atlas TCAD software breakdown behavior of gate-connected field plate (GFP), gate-source (dual) field plate, and discrete source-connected field plate (Sunken SC-FP) designs with field plate length variation is probed and physical insight is developed through electric field profile, and impact ionization contour plots. By employing a Sunken SC-FP with gate length of 0.4 μm in the gate-drain access region the device breakdown voltage is improved and has high JFOM (4.8 THz·V). Also, on-resistance (RON) degradation is minimum in the Sunken SCFP (20.12 %), compared with GFP (31.20 %) and dual FP (24.96 %) architectures, when the device is stressed in the off-state (VGS = −40 V) for 1 min. The RF performance of the Sunken SC-FP HEMT is studied using small signal parameters and the load pull measurements as a function of drain bias.

Investigation of variable field plate length in GaN HEMT on SiC substrate for MMIC applications

This work intends to improve the GaN HEMT device breakdown voltage, by uniformly distributing peak electric field using field plate engineering technique. A peak electric field reduction is observed by adding field plate at the gate end along with remolding the distribution of electric field linearly. The device breakdown voltage is improved by gradual decrease in electric field is observed. To analyze the OFF-state breakdown voltage, the gate field plate of various lengths is used and optimum size is calculated for GaN HEMTs. A breakdown voltage of 350 V is prominently observed in the simulation results. Moreover, the obtained results show a good substantiation with experimental data. The DC Characteristics and AC characteristics of the proposed structure exhibit an enhanced performance than the existing structures, justifying the GaN field plated HEMT as to be a promising solution for Microwave monolithic Integrated Circuit applications.

Improved breakdown voltage mechanism in AlGaN/GaN HEMT for RF/Microwave applications: Design and physical insights of dual field plate

This work investigated and proposed the source–gate dual field plate (SG-FP) AlGaN/GaN HEMT for different gate-to-drain drift distances with a fixed gate length of 0.25 μm using ATLAS-TCAD. The increment in the GaN buffer thickness and gate-to-drain drift distance with the variation in the field plate length improves the device performance and breakdown voltages by maintaining the impact ionization mechanism. The breakdown voltage behavior, physical insights of electric field contour, impact generation rate, and potential profile intricacies of source field plate (S-FP), gate field plate (G-FP), and dual field plate (SG-FP) are illustrated. The proposed source–gate dual field plate (SG-FP) with the SiN passivation interfacial layer, SiO2, thicker GaN buffer, and extended gate-to-source drift region is best suited for optimal performance in high breakdown voltage, with optimum cut-off frequency and low gate-leakage current. The proposed dual field plate AlGaN/GaN device with the source field plate (LS-FP = 4 μm), gate field plate (LG-FP = 2 μm), the AlGaN buffer thickness of 3.697 μm, and gate-to-drain drift distance of 8 μm show the highest breakdown voltage of 562 V with the optimum frequency of 8.861 GHz. Finally, the AC/DC characteristics of the optimized dual field plate (SG-FP) are demonstrated. We observed that the source–gate dual field plate (SG-FP) device shows a 6.70% and 4.09% improvement in breakdown voltage compared to individual source field plate (S-FP) and gate field plate (G-FP) designs, respectively. This work shows that the proposed dual field plate device is used in power switching, high-power, and RF/Microwave applications due to its superior breakdown voltage performance, reduction in parasitic capacitances, and optimal cut-off frequency.

Effect of Field Plate on Device Performance of Wide Bandgap HEMT

Background: Devices with field plates have gained much popularity in high power and high voltage applications. The work done in this paper is related to designing and studying the different DC and RF characteristics of a field plated GaN HEMT. The results obtained were compared with that of non-field plated GaN HEMT. This comparison and study reported the effect of field plate on device performance. Methods: A GaN HEMT device with and without a field plate was designed and simulated in the SILVACO ATLAS TCAD tool. The performance of both the devices was compared in terms of the exhibited DC and RF characteristics in order to study the effect of the field plate on the device. We have also studied the variation in the cut-off frequency and maximum frequency of both the field plate and without field plate GaN HEMT with respect to gate-source voltage. We have further investigated the device performance by varying the length of the field plate from 0 to 2.5 μm. Results: The study reflects the advantageous feature of GaN HEMT with field plate by exhibiting high breakdown voltage of 292 V in comparison to GaN HEMT without field plate which exhibits a breakdown voltage of 98 V. As a result of using field plate in the GaN HEMT structure, a rise in the Cgs and Cgd capacitances are witnessed. This in turn affects the other RF characteristics of the GaN HEMT with field plate even though the GaN HEMT with and without field plate exhibits nearly same DC characteristics. The field plated GaN HEMT exhibits a reduced cut-off frequency and maximum frequency of 7 GHz and 20 GHz, respectively, in comparison to the GaN HEMT without field plate’s cut-off frequency and maximum frequency of 10 GHz and 25 GHz, respectively. Conclusion: The study reports that using a field plate helps in enhancing the breakdown voltage but at the cost of reduced frequency performance. We have compared our proposed field plated device with different non-field plated devices and concluded that our device exhibits much higher breakdown voltage in spite of reduced device dimension. With the attainment of higher breakdown voltage our proposed GaN HEMT device can be used for high power applications. From the study, it is reported that while increasing the length of the field plate the breakdown voltage also increases. For a particular set of device dimensions, an optimum field plate length provides the highest breakdown voltage but increasing the length of the field plate beyond the optimum value results in reduction in breakdown voltage.

DC and RF performance of HR Si(111)-based AlGaN/GaN MIS-HEMT with a symmetrical multi-finger grid array structure for 5G N28 700MHz low-bias-control applications

HR Si(111)-based AlGaN/GaN metal insulator semiconductor high electron mobility transistor (MIS-HEMT) for 5G mobile communication at N28 700 MHz band is proposed in this paper. The device is ingeniously designed with a symmetrical dual-column multi-finger grid array structure. In addition, the device is designed with an MIS gate with a 6 nm SiN dielectric film to suppress the leakage current and a source field plate to suppress the current collapse effect. The fabrication process of the device is studied in detail, including the epitaxial surface treatment, F ion implantation isolation, ohmic contact, electron beam lithography gate process, surface passivation, and source field plate. A device with a gate length of 0.25 μm, gate-source space of 1 μm, a gate width of 1200 μm (the number of gate fingers is 12 with a single-finger gate width of 100 μm), and source field plate length of 0.2 μm is fabricated successfully. Results of electrical tests show that the HEMT device has a threshold voltage of about −7.5 V, a low knee voltage of about 4 V, a high saturation drain current density of 750 mA/mm, and a gate leakage current as low as less than 160 pA at the gate bias of 0 V. At the frequency band of 703–803 MHz, with low bias control of 10 V, the S21 of HEMT is about 5.923–7.261 dB, the gain flatness is 1.338 dB, the current gain is about 27.3 dB, and the stability factor is more than 1. This device would be a good candidate for future 5G low-frequency and low-voltage-control applications.

Investigation on Fe-Doped AlGaN/GaN HEMT at 148 GHz Using E-FPL Technology for High-Frequency Communication Systems

In this research work, design of the Extended Field Plate Length (E-FPL) T-gate with Fe doped AlGaN buffer structure on the graded Aluminum Gallium nitride (AlGaN)/ Gallium nitride (GaN) high electron mobility transistor (HEMT) is proposed. The gate length of 60 nm with an ExFPL up to 50 nm towards the drain shows remarkable improvement in breakdown voltage. Meanwhile, the drain current (IDS) and transconductance (GM) is further improved by the Fe doped AlGaN Buffer design. In radio frequency (RF) small signal analysis this device exhibits a peak current-gain cutoff frequency fT of 148 GHz. This device has improved transconductance of 24% with high frequency has compared with conventional GaN HEMT device. It is highly compatible with military applications such as Radio Frequency (RF) upstream transmitters, ship and aircraft communication transmitters and High-frequency Radars (HFRs).

Investigation of Isolation Approaches and the Stoichiometry of SiNx Passivation Layers in “Buffer‐Free” AlGaN/GaN Metal–Insulator–Semiconductor High‐Electron‐Mobility Transistors

Critical process modules for the fabrication of metal–insulator–semiconductor high‐electron‐mobility transistors (MISHEMTs) based on a novel ‘buffer‐free’ AlGaN/GaN heterostructure grown with metal–organic chemical vapor deposition (MOCVD) are presented. The methods of isolation and passivation for this type of heterostructure are investigated. Utilizing nitrogen implantation, it is possible to achieve off‐state destructive breakdown voltages (BVs) of 2496 V for gate–drain distances up to 25 μm, whereas mesa isolation techniques limit the BV below 1284 V. The stoichiometry of the SiN x passivation layer displays a small impact on the static and dynamic on‐resistance. However, MISHEMTs with Si‐rich passivation show off‐state gate currents in the range of 1–100 μA mm−1 at voltages above 1000 V, which is reduced below 10 nA mm−1 using a stoichiometric SiN x passivation layer. Destructive BVs of 1532 and 1742 V can be achieved using gate‐integrated and source‐connected field plates for MIHEMTs with stoichiometric and Si–rich passivation layers, respectively. By decreasing the field plate lengths, it is possible to achieve BVs of 2200 V. This demonstrates the implementation of MISHEMTs with high‐voltage operation and low leakage currents on a novel “buffer‐free” heterostructure by optimizing the SiN x stoichiometry.

Design of multi-channel AlGaN/GaN Schottky diode for improving rectification efficiency in microwave power transmission

Schottky barrier diode (SBD) is the core of the rectification circuit in the microwave power transmission (MPT) system and suitable for high-power RF-DC conversion. However, the rectification efficiency of current commercial SBD cannot meet the requirements of the MPT system. Therefore, this paper proposes a microwave rectification circuit based on the multi-channel AlGaN/GaN SBD. The effect of diode parameters on the rectification efficiency has been investigated, such as the number of channels, the length of anode field plate (LAFP) and the thickness of insulation layer. Simulation results show that multiple AlGaN/GaN heterojunctions can significantly reduce the on-resistance of SBD and improve the rectification efficiency. The power capacity of SBD can be increased withthe optimised LAFP and the thickness of insulation layer, which enables efficient microwave rectification in high power applications. High RF-DC rectification efficiency of 85.1% is obtained at the input power of 33 dBm. The rectification efficiency exceeds 60% over a wide input power range (14–38 dBm). The results demonstrate the great potential of multi-channel AlGaN/GaN SBD for high-power MPT application.

Analysis of Operational Characteristics of AlGaN/GaN High-Electron-Mobility Transistor with Various Slant-Gate-Based Structures: A Simulation Study.

This study investigates the operational characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) by applying a slant-gate structure and drain-side extended field-plate (FP) for improved breakdown voltage. Prior to the analysis of slant-gate-based HEMT, simulation parameters were extracted from the measured data of fabricated basic T-gate HEMTs to secure the reliability of the results. We suggest three different types of slant-gate structures that connect the basic T-gate electrode boundary to the 1st and 2nd SiN passivation layers obliquely. To consider both the breakdown voltage and frequency characteristics, the DC and RF characteristics of various slant-gate structures including the self-heating effect were analyzed by TCAD simulation. We then applied a drain-side extended FP to further increase the breakdown voltage. The maximum breakdown voltage was achieved at the FP length of 0.4 μm. Finally, we conclude that the slant-gate structures can improve breakdown voltage by up to 66% without compromising the frequency characteristics of the HEMT. When the drain-side FP is applied to a slant-gate structure, the breakdown voltage is further improved by up to 108%, but the frequency characteristics deteriorate. Therefore, AlGaN/GaN HEMTs with an optimized slant-gate-based structure can ultimately be a promising candidate for high-power and high-frequency applications.

Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages

Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an In_<i>x</i>Ga<inline-formula> <tex-math notation="LaTeX">$_{{1}-{x}}$ </tex-math></inline-formula>As channel with a Ga-composition grading (<inline-formula> <tex-math notation="LaTeX">${x} \,\,=$ </tex-math></inline-formula> 1&#x2013;0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, in VNW MOSFETs. The field plate consists of a vertically integrated SiO₂ layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 <inline-formula> <tex-math notation="LaTeX">$\Omega \cdot \mu \text{m}$ </tex-math></inline-formula>, and transconductance decrease by 5 <inline-formula> <tex-math notation="LaTeX">$\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula>, per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V.

Design and investigation of field plate-based vertical GAA – β-(AlGa)2O3/Ga2O3 high electron mobility transistor

In this work, a novel Gate-all-around β-(AlGa)2O3/Ga2O3 HEMT device with Al2O3 as a passivation layer using gate connected field plate technique has been proposed. Proposed device results in improved breakdown voltage and out power density. To investigate intensively, field plate length has been varied from 0.5 ​μm to 2.5 ​μm and effects of variation are analyzed on analog as well as linearity parameters. At 2.5 ​μm field plate length, considered device exhibited peak breakdown voltage and out power density of 915 ​V and 21.8 ​KW respectively. At proposed field plate length (=2.5 ​μm), effects of gate electrode are comprehensively investigated by varying gate length and work function. For analysis, gate length is varied from 0.5 ​μm to 1 ​μm and work function varied from 5.1eV to 6.0eV. In future, proposed device can be used in power switching applications such as telecommunication, factory automation and motor control.

Increasing the breakdown voltage in gate – Field plate High Electron Mobility Transistor using a surface field distribution layer and gate-drain edge passivation

We investigate the breakdown characteristics of AlGaN/GaN High Electron Mobility Transistor (HEMT) with surface field distribution layer (SFDL) and gate-drain edge passivation. We employ an SFDL to redistribute the surface electric field at the gate-drain edge. The combination of SFDL with gate-drain edge (Si3N4) passivation results in a considerable reduction in the peak electric field at the gate-drain edge, as well as a reduction in the HEMT device's gate-leakage current. The influence of field plate (FP) length on breakdown voltage is investigated and compared with our suggested HEMT. Our analysis reveals that the combined effect of SFDL and gate-drain edge passivation for optimized gate – Field Plate HEMT reduces the peak electric field at the gate-drain edge by five times and increases the breakdown voltage by three times.

Reduction of reverse leakage current at the TiO2/GaN interface in field plate Ni/Au/n-GaN Schottky diodes

This paper presents the fabrication procedure of TiO2 passivated field plate Schottky diode and gives a comparison of Ni/Au/n-GaN Schottky barrier diodes without field plate and with field plate of varying diameters from 50 to 300 µm. The influence of field oxide (TiO2) on the leakage current of Ni/Au/n-GaN Schottky diode was investigated. This suggests that the TiO2 passivated structure reduces the reverse leakage current of Ni/Au/n-GaN Schottky diode. Also, the reverse leakage current of Ni/Au/n-GaN Schottky diodes decreases as the field plate length increases. The temperature-dependent electrical characteristics of TiO2 passivated field plate Ni/Au/n-GaN Schottky diodes have shown an increase of barrier height within the temperature range 300…475 K.

The Influence of Design on Electrical Performance of AlGaN/GaN Lateral Schottky Barrier Diodes for Energy-Efficient Power Applications

In this paper, lateral AlGaN/GaN Schottky barrier diodes are investigated in terms of anode construction and diode structure. An original GaN Schottky diode manufacturing-process flow was developed. A set of experiments was carried out to verify dependences between electrical parameters of the diode, such as reverse and forward currents, ON-state voltage, forward voltage and capacitance, anode-to-cathode distance, length of field plate, anode length, Schottky contact material, subanode recess depth, and epitaxial structure type. It was found that diodes of SiN/Al0.23Ga0.77N/GaN epi structure with Ni-based anodes demonstrated two orders of magnitude lower reverse currents than diodes with GaN/Al0.25Ga0.75N/GaN epitaxial structure. Diodes with Ni-based anodes demonstrated lower VON and higher IF compared with diodes with Pt-based anodes. As a result of these investigations, an optimal set of parameters was selected, providing the following electrical characteristics: VON = 0.6 (at IF = 1 mA/mm), forward voltage of the diode VF = 1.6 V (at IF = 100 mA/mm), maximum reverse voltage VR = 300 V, reverse leakage current IR = 0.04 μA/mm (at VR = −200 V), and total capacitance C = 3.6 pF/mm (at f = 1 MHz and 0 V DC bias). Obtained electrical characteristics of the lateral Schottky barrier diode demonstrate great potential for use in energy-efficient power applications, such as 5G multiband and multistandard wireless base stations.

Optimized Device Geometry of Normally-On Field-Plate AlGaN/GaN High Electron Mobility Transistors for High Breakdown Performance Using TCAD Simulation

This study presents the optimization of the lateral device geometry and thickness of the channel and barrier layers of AlGaN/GaN high electron mobility transistors (HEMTs) for the enhancement of breakdown voltage (VBR) characteristics using a TCAD simulation. The effect of device geometry on the device performance was explored by varying the device design parameters, such as the field plate length (LFP), gate-to-drain length (LGD), gate-to-source length (LGS), gate length (LG), thickness of the Si3N4 passivation layer (Tox), thickness of the GaN channel (Tch), and AlGaN barrier (Tbarrier). The VBR was estimated from the off-state drain current versus the drain voltage (IDS–VDS) curve, and it exhibited a strong dependence on the length and thickness of the parameters. The optimum values of VBR for all the device’s geometrical parameters were evaluated, based on which, an optimized device geometry of the field-plated AlGaN/GaN HEMT structure was proposed. The optimized AlGaN/GaN HEMT structure exhibited VBR = 970 V at IGS = 0.14 A/mm, which was considerably higher than the results obtained in previous studies. The results obtained in this study could provide vital information for the selection of the device geometry for the implementation of HEMT structures.

On the Channel Hot-Electron’s Interaction With C-Doped GaN Buffer and Resultant Gate Degradation in AlGaN/GaN HEMTs

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances. Besides field dependence, the critical voltage was found to be carrier energy dependent by comparing the performance of devices subjected to semi- ON-state stress with devices under OFF-state stress. Experimentation on HEMTs with different buffer carbon doping variations revealed the degradation phenomenon to be a function of carbon doping in the GaN buffer. Furthermore, detailed electric field and electron temperature analysis revealed the drain edge to be a hot spot in accelerating interaction of hot electrons with traps in the GaN buffer leading to gate current degradation. A mechanism based on hot electron–buffer trap interaction-induced thermoelastic stress buildup and subsequent defect formation in the GaN buffer is proposed to explain the observed performance degradations. Observations such as a significant rise in channel temperature and accumulation of mechanical stress in the GaN buffer validate the proposed mechanism. Finally, the processes responsible for degradation lead to catastrophic failure of the device for longer stress times by the formation of cracks and pits in the GaN buffer, as validated by the postfailure field emission scanning electron microscopy (FESEM) analysis.