Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages

Abstract

Heterostructure engineering in III-V vertical nanowire (VNW) MOSFETs enables tuning of transconductance and breakdown voltage. In this work, an In_<i>x</i>Ga<inline-formula> <tex-math notation="LaTeX">$_{{1}-{x}}$ </tex-math></inline-formula>As channel with a Ga-composition grading (<inline-formula> <tex-math notation="LaTeX">${x} \,\,=$ </tex-math></inline-formula> 1&#x2013;0.4) in the channel and drain region, combined with field plate engineering, enables breakdown voltage above 2.5 V, while maintaining transconductance of about 1 mS/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, in VNW MOSFETs. The field plate consists of a vertically integrated SiO₂ layer and a gate contact, which screens the electric field in the drain region, extending the device operating voltage. By scaling the field plate, a transconductance of 2 mS/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, alongside the breakdown voltage of 1.5 V, is obtained, demonstrating the benefit of field engineering in the drain. The scalability of the field plate and the gate is measured, showing an ON-resistance increase by 23 <inline-formula> <tex-math notation="LaTeX">$\Omega \cdot \mu \text{m}$ </tex-math></inline-formula>, and transconductance decrease by 5 <inline-formula> <tex-math notation="LaTeX">$\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula>, per nm field plate length. This behavior is captured in a new and modified virtual source model, where device transmission and drain resistance are altered to capture the field plate scaling effect. The modeling is applied to nanowire (NW) devices with field plate lengths ranging from 5 to 115 nm, capturing accurately essential device performance parameters. Finally, a modified band-to-band (BTB) tunneling approach is used to accurately describe the device behavior above 1.5 V.