Field Plate Length Research Articles

Gate-structure optimization for high frequency power AlGaN/GaN HEMTs

The influence of gate-head and gate-source-spacing on the performance of AlGaN/GaN HEMTs was studied. Suggestions are then made to improve the performance of high frequency power AlGaN/GaN HEMTs by optimizing the gate-structure. Reducing the field-plate length can effectively enhance gain, current gain cutoff frequency and maximum frequency of oscillation. By reducing the field-plate length, devices with 0.35 μm gate length have exhibited a current gain cutoff frequency of 30 GHz and a maximum frequency of oscillation of 80 GHz. The maximum frequency of oscillation can be further optimized either by increasing the gate–metal thickness, or by using a τ-shape gate (the gate where the gate-head tends to the source side). Reducing the gate–source spacing can enhance the maximum drain-current and breakdown voltage, which is beneficial in enhancing the maximum output power of AlGaN/GaN HEMTs.

On-State and Off-State Breakdown Voltages in GaAs PHEMTs With Various Field-Plate and Gate-Recess Extension Structures

GaAs pseudomorphic high-electron mobility transistors (PHEMTs) with various field-plate (FP) and gate-recess (GR) extensions were fabricated. Their on-state resistance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ), breakdown voltage, flicker noise, and microwave characteristics were investigated. The FP length and GR width extensions can be controlled to improve significantly the breakdown voltage of PHEMTs. The design-of-experiment approach was employed with 16 transistors. The FP length extension was found to improve efficiently the off-state breakdown voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) because of its suppression of the thermionic-field emission of gate electrons. However, an FP-induced depletion region cannot easily suppress channel impact ionization, which dominates the on-state breakdown voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BV</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). Additionally, the FP length extension reduces the flicker noise of a device that is caused by surface states. The GR width extension has an opposite effect, because the exposed area of the uncap Schottky layer exposure increases with the GR width.

Analysis of field-plate effects on buffer-related lag phenomena and current collapse in GaN MESFETs and AlGaN/GaN HEMTs

A two-dimensional transient analysis of field-plate GaN MESFETs and AlGaN/GaN HEMTs is performed in which a deep donor and a deep acceptor are considered in a semi-insulating buffer layer, and quasi-pulsed current–voltage curves are derived from them. How the existence of a field plate affects buffer-related drain lag, gate lag and current collapse is studied. It is shown that in both MESFET and HEMT, the drain lag is reduced by introducing a field plate because electron injection into the buffer layer is weakened by it, and the buffer-trapping effects are reduced. It is also shown that the field plate could reduce buffer-related current collapse and gate lag in the FETs. The dependence of lag phenomena and current collapse on the field-plate length and on the SiN passivation layer thickness is also studied. The work suggests that in the field-plate structures, there is an optimum thickness of the SiN layer to minimize the buffer-related current collapse and drain lag in GaN MESFETs and AlGaN/GaN HEMTs.

Simulation Details for the Electrical Field Distribution and Breakdown Voltage of 0.15μThin Film SOI Power Device

The ultra-high breakdown voltage behavior of a thin-film SOI LDMOS device with a variation in the lateral doping (VLD) of drift region is analyzed extensively by TSuprem4 and Medici. The on/off state resistance and breakdown voltage depending on device parameters including drift region length, doping density gradient, and gate field plate length are examined thoroughly. The process figure of merit (FOM) has shown excellent result for devices with the optimum linearly doped drift region ranging from 30μ to 60μ. The safe operating area (SOA) for drain source current versus on-state breakdown voltage for a 60μ drift region is also presented.

Laterally engineered field‐plate GaN HEMTs for millimeter‐wave applications

AbstractA laterally Engineered Field Plate (EFP) design is implemented to obtain a field‐plated, 30 nm gate structure with a small added capacitance due to the presence of the field plate. By reducing the field plate length, and simultaneously placing it away from the gate, we are able to reduce the field plate capacitance while maintaining its effectiveness in reducing the peak electric field at the gate edge. GaN HEMT EFP devices were fabricated with 30 nm gate lengths, and 70nm field plates. A three‐terminal breakdown voltage (VBD) of 63 V was measured for the 30 nm EFP device. This VBD represents a 2x improvement over the breakdown of 100nm conventional T‐gate devices fabricated on the same wafer. The device had an extrinsic FT of 65 GHz and an FMAX of 120 GHz. Improvement in both Pout and PAE was also realized with this new gate design compared to conventional T‐gate devices. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Short-Channel AlGaN/GaN Field-Plated High-Electron-Mobility Transistors for X-Band High Power Operation

We present experimental results on the high frequency (10 GHz) operation of short-channel AlGaN/GaN field-plated high-electron-mobility transistors (FP-HEMTs). The gate-length of 0.25 µm, which is the shortest for FP-HEMTs on sapphire reported to date, has been used to extend the operation of FP-HEMTs to X-band and higher. High frequency performance of FP-HEMTs was investigated for different field-plate lengths (LFP). For LFP = 1 µm, the measured fT and fmax were 28 and 51 GHz, respectively, which is suitable for X-band operation. When LFP was increased from 0 to 1.0 µm, the breakdown voltages of the FP-HEMTs increased from 64 to 111 V giving a breakdown voltage improvement of more than 70%. In addition, leakage current did not limit the large-signal performance of the transistors resulting in excellent power-added-efficiency (PAE) of 45% under small heat dissipation condition. The FP-HEMT having LFP = 1 µm showed a small-signal gain of 11 dB and a saturated output power of 4.4 W/mm at 10 GHz.

Microwave performance of field-plate 0.13-μm MOS transistors with varying field-plate extension

Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance ( R g) resulting in the better microwave performance. By increasing the length of field-plate metal extension ( L FPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current ( I ds) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for L FPE of 0.3 μm device, and these values where 54.7% and 53.8% for L FPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.

Current collapse mechanism of field-plated AlGaN/GaN HEMTs

Current collapse restrain ability of passivated AlGaN/GaN HEMTs and AlGaN/GaN HEMTs with varying field-plate(FP) length is investigated under different drain bias. The results show that, the passivated HEMTs suffer no current collapse at relatively low but not at higher drain bias, while the HEMTs with optimal field-plate suffer no current collapse for all drain bias used in our tests. Under high drain bias, the FP length plays a crucial role in the current collapse removal. After a thoroughly analysis, it can be concluded that FP structure not only restrains the trapping of virtual gate, but also discharge the virtual gate. Finally, a discharging model of dielectric under FP is presented to explain the effect of FP length on current collapse removal.

Geometrical optimization of AlGaN/GaN field-plate high electron mobility transistor

Results of investigation on AlGaN/GaN field-plate high electron mobility transistor with different field-plate (FP) geometry are presented. The effect of the field-plate length LFP on the electric field distribution in the channel is thoroughly analyzed by establishing a simplified model. The simulation gives the following estimates: Both the FP length LFP and the thickness t of the insulator under the FP, can reshape the electric field distribution in the channel. If LFP is short, the breakdown voltage Vbr increases with LFP. When LFP increases to a certain extent, Vbr keeps invariable. After optimizing LFP in this paper, Vbr has been increased by 64%. Good agreement between experimental and simulation data is achieved.

Numerical analysis on the 4H-SiC MESFETs with a source field plate

A new structure of 4H-SiC MESFETs based on the source field plate technology is proposed in this paper. The source field plate has been applied not only to improve the breakdown voltage, but also to eliminate the drawback of low gain characteristics resulting from additional feedback capacitance associated with the field plate electrode. The off-state breakdown voltage was significantly improved by employing a source field plate electrode, and the highest value of 203 V was obtained with a source field plate length of 1.1 µm. As compared to the conventional structures, the MESFETs with a source field plate show an approximately 41% decrease in the gate-to-drain capacitance, which is responsible for the 2.2 dB gain improvement at 2 GHz. This is because the source field plate redistributes the electric fields in the gate-to-drain region and hence reduces the gate-to-drain capacitance in the intrinsic device. Therefore, the 4H-SiC MESFETs with the source field plate have superior dc and RF performances compared to similar devices based on the conventional structure.

Simulation and fabrication of high voltage AlGaN/GaN based Schottky diodes with field plate edge termination

In this paper, we report the breakdown voltage (BV) of AlGaN/GaN based Schottky diodes with field plate edge termination. Simulation and fabrication of AlGaN/GaN Schottky diodes were carried out. The simulations were performed using the commercial 2-D device simulator DESSIS. From the simulations, it is found that for a given gate-Ohmic distance ( L gd) of 10 μm, 2DEG of 1 × 10 13 cm −2 and field plate length ( L FP) of 2.5 μm, highest BV can be obtained for a silicon nitride thickness of 8000 Å and this BV value is more than 5 times that for a Schottky diode without field plate. The breakdown voltages were also simulated for different field plate lengths. The BV values obtained on the fabricated Schottky diodes are compared with the simulation data and the experimental results follow the trend obtained from the simulation. Simulations were also carried out on a Schottky diode with field plate placed over a stepped insulator with L gd = 10 μm, L FP = 5 μm and 2DEG = 1 × 10 13 cm −2 and the obtained BV values are about 7 times that without field plate.

Characterization of a self-built field-plate gate on InGaP/InGaAs heterojunction doped-channel field-effect transistors

Heterojunction doped-channel field-effect transistors (HDCFETs) with a self-built field-plate gate formation were fabricated and proposed in this work. Arrangement of Schottky metal across a step undercut between the Schottky barrier and the insulator-like layer is the key process to produce a self-built field-plate gate. A controllably reduced gate length and a self-built field plate were simultaneously formed. Effects of gate-metal length, field-plate length and insulator thickness on HDCFET performance were also investigated. Simulated results reveal that higher currents, lower electric fields, better device linearity and larger output power are expected by offsetting the Schottky metal towards the drain side. A HDCFET with gate-metal length of 0.4 µm, field-plate length of 0.6 µm and insulator thickness of 120 nm was successfully fabricated for comparison to that with a 1 µm traditional planar gate. Current density (451 mA mm−1), transconductance (225 mS mm−1), breakdown voltages (VBD(DS)/VBD(GD) = 22/−25.5 V), gate-voltage swing (2.24 V), unity current-gain and power-gain frequencies (ft/fmax = 17.2/32 GHz) are improved as compared to those of a 1 µm gate device without field plates. At 1.8 GHz and VDS of 4.0 V, maximum power-added efficiency of 36% with output power of 13.9 dBm and power gain of 8.7 dB was obtained. Saturated output power and linear power gain are 316 mW mm−1 and 13 dB, respectively.

Structure optimization of field-plate AlGaN/GaN HEMTs

AlGaN/GaN high electron mobility transistors (HEMTs) on 6H-SiC with varying field-plate length and gate–drain spacing were fabricated and analyzed. The classical small signal FET model and the well-known ColdFET method were used to extract the small signal parameters of the devices. Though the devices with field plates exhibited lower better fT characteristic, they did demonstrate better fmax, MSG and power density performances than the conventional devices without field plate. Besides, no independence of DC characteristic on field-plate length was observed. With the increase of the field-plate length and the gate–drain spacing, the characteristic of fT and fmax degraded due to the large parasitic effects. Loadpull method was used to measure the microwave power performance of the devices. Under the condition of continuous wave at 5.4GHz, an output power density of 4.69W/mm was obtained for device with field-plate length of 0.5μm and gate–drain length of 2μm.

Fabrication and characterization of field-plated buried-gate SiC MESFETs

Silicon carbide (SiC) MESFETs were fabricated using a standard SiC MESFET structure with the application of the buried-channel and field-plate (FP) techniques in the process. FPs combined with a buried-gate are shown to be favorable concerning output power density and power-added efficiency (PAE), due to higher breakdown voltage and decreased output conductance. A very high power density of 7.8 W/mm was measured on-wafer at 3 GHz for a two-finger 400-/spl mu/m gate periphery SiC MESFET. The PAE for this device was 70% at class AB bias. Two-tone measurements at 3 GHz /spl plusmn/ 100 kHz indicate an optimum FP length for high linearity operation.

Field-plated 0.25-/spl mu/m gate-length AlGaN/GaN HEMTs with varying field-plate length

Metal-organic chemical vapor deposition-grown field-plated 0.25-/spl mu/m gate-length AlGaN/GaN high-electron mobility transistors (HEMTs) with field-plate lengths of 0.5, 0.8, and 1.1 /spl mu/m have been fabricated on 6H-SiC substrates. These 0.25-/spl mu/m gate-length devices exhibited maximum drain current density of more than 1.4 A/mm and peak extrinsic transconductance of 437 mS/mm. No dependence of dc I-V as well as transfer characteristics on field-plate length was observed. With increase of field-plate length, degradation in the value of unity current gain frequency f/sub T/ and maximum frequency of oscillation f/sub max/ was observed, but there is significant improvement in breakdown voltage and power densities. Also, at 18 GHz, a continuous-wave output power density of 9.1 W/mm with power added efficiency of 23.7% was obtained for device with field-plate length of 1.1 /spl mu/m, yielding the highest reported power performance of AlGaN/GaN HEMTs at 18 GHz.

Design Optimization of High Breakdown Voltage AlGaN–GaN Power HEMT on an Insulating Substrate for&amp;lt;tex&amp;gt;$R_rm ONAhbox --V_B$&amp;lt;/tex&amp;gt;Tradeoff Characteristics

High breakdown voltage AlGaN-GaN power high-electron mobility transistors (HEMTs) on an insulating substrate were designed for the power electronics application. The field plate structure was employed for high breakdown voltage. The field plate length, the insulator thickness and AlGaN layer doping concentration were design parameters for the breakdown voltage. The optimization of the contact length and contact resistivity reduction were effective to reduce the specific on-resistance. The tradeoff characteristics between the on-resistance and the breakdown voltage can be improved by the optimization of the above design parameters, and the on-resistance can be estimated to be about 0.6 m/spl Omega//spl middot/cm/sup 2/ for the breakdown voltage of 600 V. This on-resistance is almost the same as that for the device on a conductive substrate.

LDMOS in SOI technology with very-thin silicon film

In this paper, we extensively investigate, by two-dimensional simulations, the output characteristics accuracy and breakdown voltage performance for very-thin film (80 nm) SOI lateral double-diffused MOS (LDMOS) transistor as a function of the drift doping, drift length and field plate length. Trade-offs are discussed to optimize the off-state breakdown voltage versus the occurrence of kink effect and quasi-saturation in on-state. The conclusions are supported by experimental results.

30-W/mm GaN HEMTs by Field Plate Optimization

GaN high-electron-mobility-transistors (HEMTs) on SiC were fabricated with field plates of various dimensions for optimum performance. Great enhancement in radio frequency (RF) current-voltage swings was achieved with acceptable compromise in gain, through both reduction in the trapping effect and increase in breakdown voltages. When biased at 120 V, a continuous wave output power density of 32.2 W/mm and power-added efficiency (PAE) of 54.8% at 4 GHz were obtained using devices with dimensions of 0.55/spl times/246 /spl mu/m/sup 2/ and a field-plate length of 1.1 /spl mu/m. Devices with a shorter field plate of 0.9 /spl mu/m also generated 30.6 W/mm with 49.6% PAE at 8 GHz. Such ultrahigh power densities are a dramatic improvement over the 10-12 W/mm values attained by conventional gate GaN-based HEMTs.

Analytic model for field-plate-edge breakdown of planar devices terminated with field plate and semiresistive layer

An analytic model for calculating the surface field of high-voltage devices terminated with a field plate and SIPOS layer is presented. This allows determination of the breakdown voltage at the field-plate edge in terms of the field-plate length, the effective length of the SIPOS layer, the thickness of oxide buffer layer, and the silicon doping concentration. The results show a fair agreement with the numerical simulations as well as the experimental results reported.

Design curves of breakdown voltage at field plate edge and effect of interface charge

Useful design curves of breakdown voltage are provided, which allow determination of breakdown voltage at the field plate edge in terms of field plate length, oxide thickness, and substrate doping concentration. The effect of the interface charge on the breakdown voltage is analyzed and determined also from the curves. The analytical results show a fair agreement with the two-dimensional device simulations using MEDICI as well as with the experimental results reported.