Characterization of a self-built field-plate gate on InGaP/InGaAs heterojunction doped-channel field-effect transistors

Abstract

Heterojunction doped-channel field-effect transistors (HDCFETs) with a self-built field-plate gate formation were fabricated and proposed in this work. Arrangement of Schottky metal across a step undercut between the Schottky barrier and the insulator-like layer is the key process to produce a self-built field-plate gate. A controllably reduced gate length and a self-built field plate were simultaneously formed. Effects of gate-metal length, field-plate length and insulator thickness on HDCFET performance were also investigated. Simulated results reveal that higher currents, lower electric fields, better device linearity and larger output power are expected by offsetting the Schottky metal towards the drain side. A HDCFET with gate-metal length of 0.4 µm, field-plate length of 0.6 µm and insulator thickness of 120 nm was successfully fabricated for comparison to that with a 1 µm traditional planar gate. Current density (451 mA mm−1), transconductance (225 mS mm−1), breakdown voltages (VBD(DS)/VBD(GD) = 22/−25.5 V), gate-voltage swing (2.24 V), unity current-gain and power-gain frequencies (ft/fmax = 17.2/32 GHz) are improved as compared to those of a 1 µm gate device without field plates. At 1.8 GHz and VDS of 4.0 V, maximum power-added efficiency of 36% with output power of 13.9 dBm and power gain of 8.7 dB was obtained. Saturated output power and linear power gain are 316 mW mm−1 and 13 dB, respectively.