Field Limiting Ring Research Articles

Design and Optimization of High Performance Multi-Step Separated Trench 4H-SiC JBS Diode

In this paper, a novel 3300 V/40 A 4H-SiC junction barrier Schottky diode (JBS) with a multi-step separated trench (MST) structure is proposed and thoroughly investigated using TCAD simulations. The results show that the introduction of MST expands the Schottky contact area, resulting in a decrease in the forward voltage drop. Furthermore, the combination of the deep P+ shielded region and the central P+ region effectively reduces the leakage current, leading to a 43.7% increase in the blocking voltage compared to conventional 4H-SiC JBS. The effects of the step depth (ds) and the width of the central P+ region (wm) on the device performance are analyzed in depth. In addition, a multi-step trenched linearly graded field-limiting rings (MTLG-FLR) termination ensures a more uniform electric field distribution, and the terminal protection efficiency reaches up to 90%, which further enhances the reliability of the terminal structure.

Total Ionizing Dose (TID) Effects on the 1.2 kV SiC MOSFETs under Proton Irradiation

In this paper, the effects of various proton irradiation energies and doses on the electrical characteristics of SiC MOSFETs have been evaluated and characterized using a proton accelerator. The devices under test were designed, fabricated and packaged using 1.2 kV/0.6 µm-tech SiC MOSFET processes. The results demonstrate that the threshold voltage (Vth) of the irradiated devices shifted towards negative values due to the radiation-induced positive oxide trapped charges. Moreover, this negative shift in Vth and positive trapped charges of field limiting ring (FLR) oxide led to an increase in output currents and a reduction in the breakdown voltage values.

An Innovative and Efficient Approach for Field-Limiting Ring Design of Power Devices Based on Deep Neural Networks

An Innovative and Efficient Approach for Field-Limiting Ring Design of Power Devices Based on Deep Neural Networks

Comparison in radiation tolerance between FLR planar junction termination and positive bevel edge termination for power diodes

In this paper, a coupled electro-thermal simulation model is established to investigate the single event burnout (SEB)-induced failure in power diode. The radiation tolerance of the two different termination structures, the field limiting ring (FLR) planar junction termination and the positive bevel edge termination, is revealed comparatively. Firstly, through the comparison in the SEB threshold voltage, our simulation results indicate that the positive bevel edge termination exhibits a stronger robustness to SEB. The difference in the anti-radiation performance can even reach 29.02% under the same ion incidence condition. Then, to fully understand why there is such a large difference in the radiation tolerance, we observed the entire failure process and obtained the SEB mechanism for the two termination structures. For the FLR planar junction termination, the edge of the main junction is the most sensitive region to SEB, since the high electric field here caused by the junction curvature effect can easily lead to the strong carrier multiplication and a large localized current density. By contrast, for the positive bevel edge termination, the electric field can be effectively reduced along the beveled surface, therefore, there is no electric field crowding at the edge of the pn junction. As a result, the positive bevel edge termination naturally exhibits a superior anti-radiation performance compared to the FLR planar junction termination structure.

Single Event Burnout Hardening Technique for High-Voltage p-i-n Diodes With Field Limiting Rings Termination Structure

High-voltage p-i-n diodes for space applications are sensitive to single event burnout (SEB), which may cause the failure of the entire electronic system. This article describes the SEB failure mechanism of high-voltage p-i-n diodes with field limiting rings (FLRs) termination structure, based on the electro-thermal coupled transient simulation model in the Sentaurus TCAD simulator. The simulation results show that the catastrophic failures result from the intense local heating at the edge of the main junction, because the high electric field strength at this region induces strong impact ionization of the charge carriers. The strike at the edge of the main junction shows the strongest sensitivity to SEB since the energetic particle-induced carriers are deposited exactly at the high electric field region. Then, a novel SEB hardening technique of localized carrier lifetime control at the edge of the main junction region is proposed based on the analysis on the failure mechanism. Our simulation results demonstrate that the reduction of the localized carrier lifetime can alleviate the peak electric field and reduce the local heat accumulation, thereby improving the SEB performance of high-voltage p-i-n diodes.

Design and demonstration of nearly-ideal edge termination for GaN p–n junction using Mg-implanted field limiting rings

A nearly-ideal edge termination for GaN p–n junctions was designed and demonstrated using Mg-ions implanted field limiting rings (FLRs). The FLRs were fabricated via the ultra-high-pressure annealing process after implanting Mg-ions into the etched n-type region outside the main p–n junction. The results of the technology computer-aided design simulation indicate that by optimizing the space and width of the rings, the breakdown voltage (BV) can be increased by over 90% of the ideal parallel plane BV (973 V). Accordingly, the fabricated diodes exhibited low leakage current and a BV of 897 V (92% of the ideal BV).

β-Ga2O3 vertical heterojunction barrier Schottky diodes terminated with p-NiO field limiting rings

In this Letter, high-performance β-Ga2O3 vertical heterojunction barrier Schottky (HJBS) diodes have been demonstrated together with the investigation of reverse leakage mechanisms. In HJBS configurations, NiO/β-Ga2O3 p-n heterojunctions and p-NiO field limiting rings (FLRs) are implemented by using a reactive sputtering technique at room temperature without intentional etching damages. Determined from the temperature-dependent current-voltage characteristics, the reverse leakage mechanism of the HJBS diode is identified to be Poole-Frenkel emission through localized trap sates with an energy level of EC-0.72 eV. With an uniform FLR width/spacing of 2 μm in HJBS, a maximum breakdown voltage (BV) of 1.89 kV and a specific on-resistance (Ron,sp) of 7.7 mΩ·cm2 are achieved, yielding a high Baliga's figure-of-merit (FOM, BV2/Ron,sp) of 0.46 GW/cm2. The electric field simulation and statistical experimental facts indicate that the electric field crowding effect at device edges is greatly suppressed by the shrinkage of p-NiO FLR spacing, and the capability of sustaining high BV is enhanced by the NiO/β-Ga2O3 bipolar structure, both of which contribute to the improved device performance. This work makes a significant step to achieve high performance β-Ga2O3 power devices by implementing alternative bipolar structures to overcome the difficulty in p-type β-Ga2O3.

Design and Fabrication of 1.2 kV/10A 4H-SiC Junction Barrier Schottky Diodes with High Current Density

This paper presents an overall optimization procedure and the electrical performances of 1.2 kV/10 A 4H-SiC junction barrier Schottky (JBS) diodes with high current density. To achieve high current density, the epi-layer, the design parameters for active region including p-grid width and cell pitch, and the field limiting ring for edge termination were optimized with analytic calculation to estimate forward electrical performances and with Silvaco atlas™ simulator to estimate reverse electrical performances. Based on the systematic design, the JBS diodes were fabricated and electrically characterized. The experimental results showed that the breakdown voltage (BV) of JBS diode was significantly sensitive to field limiting ring (FLR) space and that the JBS diode with the ratio of pure Schottky contact area to total active area of 0.75 and the FLR space of 1.25 μm had optimum electrical performances such as a forward current density of 370 A/cm2, a reverse leakage current below 20 μA at the reverse anode voltage of 1.2 kV, and the BV of 1400 V. These were in coincidence with the simulation results within 10% error.

Edge Termination With Enhanced Field-Limiting Rings Insensitive to Surface Charge for High-Voltage SiC Power Devices

An edge termination structure with enhanced field-limiting rings (enhanced FLRs) is proposed to stabilize the breakdown voltage against the surface charge. The pitches of the enhanced rings are designed to mitigate the electric field and expand the depletion layer, which leads to an improvement of the breakdown voltage. In addition, the enhanced FLR is insensitive to surface charge because the field plates completely cover the n− layer. Simulation results indicated that the enhanced FLR did not have any fluctuation of breakdown voltage against surface charge density from 0 to ${1}\times {10}^{{13}}\,\,\text {cm}^{{-}{2}}$ , whereas conventional structures did have fluctuation. To examine the validity of the concept, we fabricated a silicon carbide (SiC) merged p-i-n Schottky diode with the proposed structure. DC bias stress tests at 150 °C over 1000 h demonstrated the breakdown voltage stability of the enhanced FLR.

Reverse-Bias Stress-Induced Electrical Parameters Instability in 4H-SiC JBS Diodes Terminated Nonequidistance FLRs

In this article, the breakdown voltage ( ${V}_{\text {BR}}$ ) shift of 4H-SiC Junction Barrier Schottky (JBS) diodes terminated by optimum nonequidistant field limiting rings (FLRs) subject to reverse-bias stress (RBS) has been investigated, and the corresponding mechanisms are studied in-depth. It can be observed that ${V}_{\text {BR}}$ gradually increases with increasing stress time, but there is no obvious shift of the forward voltage ( ${V}_{F}$ ). The increment in the magnitude of ${V}_{\text {BR}}$ induced by RBS testing is shown to depend strongly on the degree of applied reverse-bias voltage. The physical mechanism of ${V}_{\text {BR}}$ shift has been investigated and explained by means of numerical technical computer-aided design (T-CAD) simulations. Our analysis shows that the hole injection and trapping into SiO2 at the FLR terminal area are identified to be the main cause, resulting in the increase of ${V}_{\text {BR}}$ . Besides, a simple model is proposed to explain the behavior of ${V}_{\text {BR}}$ instability.

Effects of proton radiation on field limiting ring edge terminations in 4H–SiC junction barrier Schottky diodes

In this study, the effects of high-energy proton radiation on the effectiveness of edge terminations using field limiting rings (FLRs) in 4H–SiC junction barrier Schottky (JBS) diodes were examined in detail. The devices were irradiated using 5-MeV protons at fluences ranging from 5× 1012 cm−2 to 5× 1014 cm−2. Further, the reverse breakdown performances of the investigated devices were measured both before and after irradiation. Proton irradiation initially decreased the breakdown voltage (BV); subsequently, the BV was increased as the proton fluence increased. At a fluence of 5× 1013 cm−2, the BV was reduced by approximately 18%, whereas it was reduced by approximately 5% at a higher proton fluence of 5× 1014 cm−2. The related degradation mechanism that was associated with this phenomenon was also investigated using the numerical simulations of the current-voltage ( I - V ) and capacitance-voltage ( C - V ) characteristics of the device. The main contribution to the radiation-induced changes in BV originates from the variations of charge distribution at the SiO2/4H–SiC interface and the reduction of the net carrier density in the drift region. Both the aforementioned variations affect the spread of the electric field in the FLR edge termination regions.

Impact of design and process variation on the fabrication of SiC diodes

We have studied the influence of design and process variations on the electrical performance of SiC Schottky diodes. On the design side, two design variations are used in the active cell of the diode (segment design and stripe design). In addition, there are two more design variations employed for the edge termination layout of the diodes, namely, field limiting ring (FLR) and junction termination extension (JTE). On the process side, some diodes have gone through an N2O annealing step. The segment design resulted in a lower forward voltage drop (VF) in the diodes and the FLR design turned out to be a better choice for blocking voltages, in the reverse bias. Also, N2O annealing has shown a detrimental effect on the diodes’ blocking performance, which have JTE as their termination design. It degrades the blocking capability of the diodes significantly.

Effect of Design Variations and N<sub>2</sub>O Annealing on 1.7kV 4H-SiC Diodes

In this work we have studied the influence of design and process variations on electrical performance of 1.7 kV 4H-SiC Schottky diodes. Diodes with two variations in their active region design namely, stripe design and segment design, were fabricated in this study. Field Limiting Rings (FLRs) or Junction Termination Extension (JTE) were used as edge termination design to achieve a blocking voltage of 1.7 kV. In addition to these designs an extra processing step of nitrous oxide (N2O) annealing was performed on some of the diodes. The study has shown that there is no extra beneficial effect of nitrous oxide annealing on device characteristics.

Experimental study on the 4H-SiC-based VDMOSFETs with lightly doped P-well field-limiting rings termination

A lightly doped P-well field-limiting rings (FLRs) termination on 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) has been investigated. Based on the simulation, the proposed termination applied to 4H-SiC VDMOSFET could achieve an almost same breakdown voltage (BV) and have the advantage of lower ion-implantation damage comparing with P+ FLRs termination. Meanwhile, this kind of termination also reduces the difficulty and consumption of fabrication process. 4H-SiC VDMOSFETs with lightly doped P-well (FLRs) termination have been fabricated on 10μm thick epi-layer with nitrogen doping concentration of 6.2×1015cm−3. The maximum breakdown voltage of the 4H-SiC VDMOSFETs has achieved as high as 1610V at a current of 15μA, which is very close to the simulated result of 1643V and about 90% of the plane parallel breakdown voltage of 1780V. It is considered that P-well FLRs termination is an effective, robust and process-tolerant termination structure suitable for 4H-SiC VDMOSFET.

Novel Designed SiC Devices for High Power and High Efficiency Systems

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density (Dit) of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , which causes the high channel mobility of 80 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> results in very low channel resistance. The buried p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 mQ cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm × 6 mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 mQ cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the blocking voltage of 3850 V are obtained for 3300 V application.

Study on geometry of silicon PIN radiation detector for breakdown voltage improvement

The silicon PIN radiation detectors are always used under high working voltages. The breakdown voltage improvement has been researched in this paper. The resistivity of the silicon is larger than 20,000 Ω cm and the thickness is 1 mm. The field plate and field-limiting ring as well as round corners are applied for comprehensive improvement. The impact of field limiting ring distance to the main junction is tested by varying the ring distance from 30 μm to 260 μm. The simulation research on ring distance is carried out. The round corner radius is researched by varying the radius from 30 μm to 500 μm.

A snapback suppressed reverse-conducting IGBT with built-in diode by utilizing edge termination

A reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with anti-parallel built-in diode in edge termination region is proposed. In the view of the cross section structure of the RC-IGBT, the Field Limiting Ring (FLR) and the equipotential ring act as an anode emitter and the N-Collector acts as the cathode emitter of the diode. In the aspect of layout, the anti-parallel built-in diode is integrated in the termination region which surrounds around the active cell region. Compared with the conventional RC-IGBT which integrates diode in active cell region, the proposed device can eliminate the snapback easily and conduct current uniformly at forward conduction of IGBT mode, which are favorable to the increase of conducting capability and the reliability. In addition, the forward voltage drop can be decreased largely, which is favorable to the decrease of conducting energy loss.

Blocking Characteristics of 2.2 kV and 3.3 kV-Class 4H-SiC MOSFETs with Improved Doping Control for Edge Termination

Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm2 for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.

Research on high-voltage 4H—SiC P—i—N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension (JTE) and offset field plates and field-limiting rings for the 4H—SiC P—i—N diode were investigated and optimized by using a two—dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H—SiC P—i—N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 × 10−5 A/cm2.

An Improved Methodology for the CAD Optimization of Multiple Floating Field-Limiting Ring Terminations

We derive an efficient and accurate computer-aided-design-based design methodology for the optimization of floating field-limiting ring terminations. The proposed approach is based on an iterative optimization of the ring-to-ring spacings starting from the outermost ring and proceeding back toward the main junction. Physics-based simulations show that each optimization step does not impair the previous one, thus allowing to easily identify the minimum number of rings needed to achieve the desired termination efficiency yet minimizing the number of simulation steps. The accuracy of the method is thoroughly discussed on the basis of comparisons against either literature results or experimental data.