Field-effect Transistor Memory Research Articles

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Effect of thickness of polymer electret on charge trapping properties of pentacene-based nonvolatile field-effect transistor memory

In this report, a set of pentacene-based organic field-effect transistor (OFET) memory devices using different thicknesses (ranged from 17.8 to 100.4 nm) of Poly (N-vinylcarbazole) (PVK) as charge trapping layers were fabricated, and the dependences of thickness on charge trapping behaviors were systematically investigated. As the thickness increased, the charge trapping capacity shows a Gaussian distributed growth behavior while the surface tunneling distance demonstrates the property of exponential decrease, which is ascribed to the synergistic effects of potential redistribution of trapped charge carriers and the co-existence of direct tunneling and Fowler–Nordheim (FN) tunneling. The optimum thickness (dot) to possess the most efficient charge trapping properties, which means a reasonably low programming voltage and high charge trapping capacity with good bias stress stability, is approximately 40 ± 5 nm. By calculating the threshold thickness (dth) of PVK for an ultrathin memory, we proposed a model of superficial tunneling distance to deconstruct the continuous chargeable polymer electret-based OFET memory. Our work provided a quantitative evaluation method and can improve the understanding of charge trapping process from the aspect of electret thickness.

Nanoionics-Based Three-Terminal Synaptic Device Using Zinc Oxide.

Artificial synaptic thin film transistors (TFTs) capable of simultaneously manifesting signal transmission and self-learning are demonstrated using transparent zinc oxide (ZnO) in combination with high κ tantalum oxide as gate insulator. The devices exhibit pronounced memory retention with a memory window in excess of 4 V realized using an operating voltage less than 6 V. Gate polarity induced motion of oxygen vacancies in the gate insulator is proposed to play a vital role in emulating synaptic behavior, directly measured as the transmission of a signal between the source and drain (S/D) terminals, but with the added benefit of independent control of synaptic weight. Unlike in two terminal memristor/resistive switching devices, multistate memory levels are demonstrated using the gate terminal without hampering the signal transmission across the S/D electrodes. Synaptic functions in the devices can be emulated using a low programming voltage of 200 mV, an order of magnitude smaller than in conventional resistive random access memory and other field effect transistor based synaptic technologies. Robust synaptic properties demonstrated using fully transparent, ecofriendly inorganic materials chosen here show greater promise in realizing scalable synaptic devices compared to organic synaptic and other liquid electrolyte gated device technologies. Most importantly, the strong coupling between the in-plane gate and semiconductor channel through ionic charge in the gate insulator shown by these devices, can lead to an artificial neural network with multiple presynaptic terminals for complex synaptic learning processes. This provides opportunities to alleviate the extreme requirements of component and interconnect density in realizing brainlike systems.

(Invited) Multi-Bit Transistor Memories Made from Mechanically Exfoliated WSe2 and Plasma-Doped MoS2

It is still desirable to explore new simple nano/microfabrication approaches that can create low-cost solid-state drives (SSDs) based on field-effect transistor (FET) memories. 2D semiconducting layered transition metal dichalcogenides (TMDCs, e.g., MoS2 and WSe2) are anticipated to provide new opportunities in this research area[1][2]. However, most recent efforts have been focused on the direct application of TMDC FET channels into the conventional FET-based memory structure consisting of regular floating gates, tunnel barriers, or charge trapping layers.[3][4] Such memory devices still have quite complicated architectures, and such works have not effectively reduced the complexity and cost of solid-state memory manufacturing. Recently, we found that an exfoliated multilayer MoS2 flake (Fig. 1a), after a plasma doping process, has a rough (or rippled) top layer (Fig. 1b). When incorporated into a FET structure (Fig. 1c), this rough layer can serve as a charge-trapping layer interfacing with the underlying pristine layers that serve as the FET channel. This device structure can function as a FET memory and enable multi-bit data storage (i.e., year-scale binary or 2-bit data storage; day-scale 3-bit data storage (see Fig. 1d)).2 This work has preliminarily leveraged the unique layered structure of TMDCs for making ultra-low-cost memory devices. Here, we further report that a mechanically exfoliated multilayer WSe2 flake can directly serve as a FET memory channel with no need of plasma doping and enable multi-bit data storage functionality. This finding could further simplify the fabrication steps for producing SSDs. The newly observed memory states in multilayer WSe2 are tentatively attributed to the vulnerability of WSe2 layers to mechanical exfoliation. This means that the mechanical exfoliation of a multilayer WSe2 flake from a bulk WSe2 stamp could directly result in a rough (or rippled) top layer on the exfoliated flake, as illustrated in Fig. 2a. Such a rough WSe2 top layer, similar to the plasma-doped MoS2 top layer illustrated in Fig. 1b, could serve as a charge-trapping layer for the FET memory and enable multi-bit data storage (Fig. 2b). Fig. 2c shows the retention characteristics of a set of 2-bit (i.e., 4 data levels) memory states measured from a representative WSe2 FET memory, which are comparable to the memory states obtained from a plasma-doped MoS2 FET memory (Fig. 1d). To support our hypothesis, we further characterized as-exfoliated WSe2 and MoS2 flakes using atomic force microscopy (AFM) (Fig. 3). The AFM results show that as-exfoliated multilayer WSe2 flakes exhibit a much larger surface roughness in comparison with as-exfoliated multilayer MoS2 flakes. Furthermore, the transmission electron micrograph (TEM) of exfoliated WSe2 layers exhibit clear Moire patterns, which implies the formation of rippled layers on top of mechanically exfoliated WSe2 flakes. These characterization results strongly support our hypothesis on the exfoliation-induced memory states in multilayer WSe2. Additional work will be performed to understand the physical origin of the vulnerability of WSe2 layers to mechanical exfoliation and evaluate the reliability/uniformity of multilayer WSe2 FET memories. In addition to advance the fabrication technology for producing low-cost memories, this work also provides important scientific insights for creating new nanoelectronic devices through mechanically processing emerging layered materials. [1] Sangwan, Vinod K, et al. Nature nanotechnology 10.5 (2015): 403-406. [2] Chen, Mikai, et al.ACS nano 8.4 (2014): 4023-4032. [3] Choi, Min Sup, et al. Nature communications 4 (2013): 1624. [4] Jariwala, Deep, et al. ACS nano 8.2 (2014): 1102-1120. Figure Captions: Figure 1: Illustrations of (a) an as-exfoliated multilayer MoS2 flake with a smooth top layer, (b) a plasma-doped MoS2 flake with a rough (or rippled) top layer, and (c) a FET memory with the plasma-doped MoS2 flake as the FET channel. (d) displays the retention characteristics of 2-bit data storage states in a typical FET memory made from a plasma-doped multilayer MoS2 flake. Figure 2: Illustrations of (a) an as-exfoliated multilayer WSe2 flake with a rough (or rippled) top layer, and (b) a FET memory with the exfoliated WSe2 flake as the FET channel. (c) displays the retention characteristics of 2-bit data storage states in a typical FET memory made from an as-exfoliated multilayer WSe2 flake. Figure 3: AFM images of the top surfaces of (a) an as-exfoliated multilayer WSe2 flake and (b) an as-exfoliated multilayer MoS2 flake. The WSe2 flake exhibits a much larger top surface roughness (RMS value: 5.6 nm) in comparison with the MoS2 flake (RMS value: 2.7 nm). Figure 4: TEM image of the top surfaces of an as-exfoliated multilayer WSe2 flake, which exhibits clear Moire patterns. Figure 1

Fluorinated p-n type copolyfluorene as polymer electret for stable nonvolatile organic transistor memory device

In this study, a kind of fluorinated copolyfluorene, named poly[(4-(octyloxy)-9,9-diphenylfluorene-2,7-diyl)-alt-(2,3,5,6-tetrafluoro-1,4-phenylene)] (PODPF-TFP), is synthesized by facile palladium-based direct aromatization. Compared to the non-fluorinated counterpart, poly[(4-(octyloxy)-9,9-diphenylfluorene-2,7-diyl)-alt-(p-phenylene)] (PODPF-P), deeper HOMO/LUMO energy level combined with steric hindrance effect endow PODPF-TFP with excellent spectra and morphology stability. Finally, organic field-effect transistor (OFET) memory devices are fabricated with PODPF-P/PODPFTFP as the dielectric layers, and they both exhibit flash type storage characteristic. Owing to the electronegativity of fluorine atom, the device based on PODPF-TFP exhibits larger memory window and more stable I on/I off ratio during a retention time of 104 s as well as a better aging stability. The present study suggests that fluorinated p-n copolyfluorene electrets could enhance the capabilities of charge trapping and storage, which are promising for OFET memory devices.

Synergistic Effects of Self-Doped Nanostructures as Charge Trapping Elements in Organic Field Effect Transistor Memory.

Despite remarkable advances in the development of organic field-effect transistor (OFET) memories over recent years, the charge trapping elements remain confined to the critical electrets of polymers, nanoparticles, or ferroelectrics. Nevertheless, rare reports are available on the complementary advantages of different types of trapping elements integrated in one single OFET memory. To address this issue, we fabricated two kinds of pentacene-based OFET memories with solution-processed amorphous and β-phase poly(9,9-dioctylfluorene) (PFO) films as charge trapping layers, respectively. Compared to the amorphous film, the β-PFO film has self-doped nanostructures (20-120 nm) and could act as natural charge trapping elements, demonstrating the synergistic effects of combining both merits of polymer and nanoparticles into one electret. Consequently, the OFET memory with β-PFO showed nearly 26% increment in the storage capacity and a pronounced memory window of ∼45 V in 20 ms programming time. Besides, the retention time of β-PFO device extended 2 times to maintain an ON/OFF current ratio of 10(3), indicating high bias-stress reliability. Furthermore, the β-PFO device demonstrated good photosensitivity in the 430-700 nm range, which was attributed to the additive effect of smaller bandgap and self-doped nanostructures of β-phase. In this regard, the tuning of molecular conformation and aggregation in a polymer electret is an effective strategy to obtain a high performance OFET memory.

High Performance Nonvolatile Transistor Memories Utilizing Functional Polyimide-Based Supramolecular Electrets.

We report pentacene-based organic field-effect transistor memory devices utilizing supramolecular electrets, consisting of a polyimide, PI(6FOH-ODPA), containing hydroxyl groups for hydrogen bonding with amine functionalized aromatic rings (AM) of 1-aniline (AM1), 2-naphthylamine (AM2), 2-aminoanthracene (AM3), and 1-aminopyrene (AM4). The effect of the phenyl ring size and composition of AM1-AM4 on the hole-trapping capability of the fabricated devices was investigated systematically. Under an operating voltage under ±40 V, the prepared devices using the electrets of 100 % AM1-AM4/PI ratios exhibited a memory window of 0, 8.59, 25.97, and 29.95 V, respectively, suggesting that the hole-trapping capability increased with enhancing phenyl ring size. The memory window was enhanced as the amount of AM in PI increased. Furthermore, the devices showed a long charge-retention time of 10(4) s with an ON/OFF current ratio of around 10(3) -10(4) and multiple switching stability over 100 cycles. This study demonstrated that the electrical characteristics of the OFET memory devices could be manipulated through the chemical compositions of the supramolecular electrets.

The effect of porous structure of PMMA tunneling dielectric layer on the performance of nonvolatile floating-gate organic field-effect transistor memory devices

In this paper, we used the low and high density porous structure of polymethylmethacrylate (PMMA) film as tunneling dielectric layer in the floating-gate organic field-effect transistor (OFET) memory devices. Compared to the thin/thick nonporous structure of PMMA tunneling layer, the porous structure of PMMA tunneling layer had positive impacts on the device performance of the floating-gate OFET memory devices. Moreover, it was found that the memory performance was also increased as pore density of PMMA film increased. The atomic force microscopy (AFM) results of both porous structure of PMMA film and pentacene film on porous structure of PMMA film revealed that high density porous structure of PMMA tunneling layer can produce larger tunneling area and more electron transfer paths between pentacene film and PMMA film, which resulted in high electron capture and release efficiency of the floating-gate OFET memory devices with porous structure of PMMA tunneling layer. In addition, our porous structure of PMMA tunneling layer as well as nonporous PMMA film has high electrical insulating property due to their semi-hollow structure film, which is favourable to maintain stable retention property. Eventually, the floating-gate OFET memory devices with high density porous structure of PMMA tunneling layer showed good nonvolatile memory properties with a large memory window of about 43 V, a high ON/OFF current ratio of about 104, and stable endurance and retention properties. Our results provided a new strategy to achieve the high performance floating-gate OFET memory devices.

Analysis of temperature-dependent electrical transport properties of nonvolatile organic field-effect transistor memories based on PMMA film as charge trapping layer

The temperature-dependent electrical transport properties of nonvolatile organic field-effect transistor (OFET) memories with Poly (methyl methacrylate) (PMMA) as a charge trapping layer were characterized at four typical temperatures (20 °C, 60 °C, 80 °C and −78.5 °C). It was found that the OFET memories showed strong temperature dependence. The performance degradations, including the memory windows and the retention characteristics, could be observed at both high and low temperatures. The degradations of the OFET memories at 60 °C, 80 °C and −78.5 °C were attributed to both the less electrons trapped by the PMMA film and the easier release of the trapped electrons from the PMMA film, which is caused by the lower crystallinity of pentacene film and the larger contact area between pentacene film and PMMA film, respectively.

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 103 between the two binary states. Programmed data could be retained for 103 s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.

Dose-rate sensitivity of deep sub-micro complementary metal oxide semiconductor process

Enhancing low dose rate sensitivity (ELDRS) in bipolar device is a major problem of liner circuit radiation hardness prediction for space application. ELDRS is usually attributed to space-charge effect. A key element is the difference in transport rate between holes and protons in SiO2. Interface-trap formation at high dose rate is reduced due to positive charge buildup in the Si/SiO2 interfacial region (due to the trapping of holes and/or protons) which reduces the flow rates of subsequent holes and protons (relative to the low-dose-rate case) from the bulk of the oxide to the Si/SiO2 interface. Generally speaking, the dose rate of metal oxide semiconductor (MOS) device is time dependent when annealing of radiation-induced charge is taken into account. The degradation of MOS device induced by the low dose rate irradiation is the same as that by high dose rate when annealing of radiation-induced charge is taken into account. However, radiation response of new generation MOS device is dominated by charge buildup in shallow trench isolation (STI) rather than gate oxide as older generation device. Unlike gate oxides, which are routinely grown by thermal oxidation, field oxides are produced using a wide variety of deposition techniques. As a result, they are typically thick (100 nm), soft to ionizing radiation, and electric field is far less than that of gate oxide, which is similar to the passivation layer of bipolar device and may lead to ELDRS. Therefore, dose-rate sensitivities of n-type metal oxide semiconductor field effect transistor (NMOSFET) and static random access memory (SRAM) manufactured by 0.18 m complementary metal oxide semiconductor (CMOS) process are explored experimentally and theoretically in this paper. Radiation-induced leakages in NMOSFET and SRAM are examined each as a function of dose rate. Under the worst-case bias, the degradation of NMOSFET is more severe under the low dose rate irradiation than under the high dose rate irradiation and anneal. Moreover, radiation-induced standby current rising in SRAM is more severe under the low dose rate irradiation than under the high dose rate irradiation even when anneal is not considered. The above experimental results reveal that the dose-rate sensitivity of deep sub-micron CMOS process is not related to time-dependent effects of CMOS devices. Mathematical description of the combination between enhanced low dose-rate sensitivity and timedependent effects as applied to radiation-induced leakage in NMOSFET is developed. It has been numerically found that non time-dependent effect of deep sub-micron CMOS device arises due to the competition between enhanced low dose-rate sensitivity in bottom of STI and time-dependent effect at the top of STI. The high dose rate irradiation is overly conservative for devices used in a low dose rate environment. The test method provides an extended room temperature anneal test to allow leakage-related parameters that exceed postirradiation specifications to return to a specified range.

Light-responsive spiropyran based polymer thin films for use in organic field-effect transistor memories

Spiropyran-based polyimide compounds have been synthesized and utilized as polymer electret thin films for application in light-responsive organic field-effect transistor memories.

Plasma treatment introduced memory properties in MoS2 field-effect transistors

We present a facile method to obtain MoS2-based nonvolatile memory field-effect transistors by oxygen plasma treatment on the MoS2 surface that is in contact with a dielectric. The oxygen plasma treatment provides a way of introducing deep defects into the MoS2 surface. Only those deep defects located at the semiconductor/dielectric interface can behave as charge trapping sites to develop the memory capability. No memory properties can be observed when the MoS2 surface far from the conductive channel was treated with oxygen plasma. This method brings promising advantages to MoS2-based memory devices obtained using a simple fabrication method and small device dimensions.

Photo-reactive charge trapping memory based on lanthanide complex.

Traditional utilization of photo-induced excitons is popularly but restricted in the fields of photovoltaic devices as well as photodetectors, and efforts on broadening its function have always been attempted. However, rare reports are available on organic field effect transistor (OFET) memory employing photo-induced charges. Here, we demonstrate an OFET memory containing a novel organic lanthanide complex Eu(tta)3ppta (Eu(tta)3 = Europium(III) thenoyltrifluoroacetonate, ppta = 2-phenyl-4,6-bis(pyrazol-1-yl)-1,3,5-triazine), in which the photo-induced charges can be successfully trapped and detrapped. The luminescent complex emits intense red emission upon ultraviolet (UV) light excitation and serves as a trapping element of holes injected from the pentacene semiconductor layer. Memory window can be significantly enlarged by light-assisted programming and erasing procedures, during which the photo-induced excitons in the semiconductor layer are separated by voltage bias. The enhancement of memory window is attributed to the increasing number of photo-induced excitons by the UV light. The charges are stored in this luminescent complex for at least 104 s after withdrawing voltage bias. The present study on photo-assisted novel memory may motivate the research on a new type of light tunable charge trapping photo-reactive memory devices.

Solution-processed dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene transistor memory based on phosphorus-doped silicon nanoparticles as a nano-floating gate

High-performance organic field-effect transistor (OFET) memories were developed by a simple solution process using phosphorus-doped silicon nanoparticles (Si NPs) and dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) precursor–polystyrene (PS) blends. Si NPs were doped with phosphorus to control the ionization potential and functioned as a nano-floating gate. DNTT precursor–PS blends were converted to DNTT/PS layers on a Si NP layer by thermal annealing. The OFET memories clearly exhibited a memory window of 20 V and a notably large threshold voltage (Vth) shift of 40 V after the application of negative and positive voltages to the gate electrode.

Zno field-effect transistors with lead-zirconate-titanate ferroelectric gate

Ferroelectric lead-zirconate-titanate [Pb(Zr0·53Ti0·47)O3] thin films with remnant polarisation and large dielectric constant have been employed in non-volatile field-effect transistor memories as gate dielectrics. Oxide semiconductor-zinc oxide (ZnO) is introduced as the channel layer because of its low crystallization temperature, good integration with different materials and low costs. In this paper, field-effect transistors using ZnO as the channel and lead-zirconate-titanate as the gate dielectric have been fabricated and characterised. Lead-zirconate-titanate and ZnO films were deposited by Sol-Gel and radio frequency (RF)-sputtering methods, respectively. Typical n-channel properties with clear current saturation in drain current v. drain voltage (Ids-Vds) characteristics have been obtained. The transfer characteristics (source-drain current v. gate voltage, Ids-Vgs) exhibited a significantly hysteresis behaviour because of the ferroelectric polarisation properties of the lead-zirconate-titanate gate dielectric. The characteristics of ferroelectric layer inducing channel electron transport properties modulation and hysteresis behaviours in ZnO-lead-zirconate-titanate structured field-effect transistors can be used for future non-volatile memory applications.

Low voltage and time constant organic synapse-transistor

We report on an artificial synapse, an organic synapse-transistor (synapstor) working at 1V and with a typical response time in the range 100–200ms. This device (also called NOMFET, Nanoparticle Organic Memory Field Effect Transistor) combines a memory and a transistor effect in a single device. We demonstrate that short-term plasticity (STP), a typical synaptic behavior, is observed when stimulating the device with input spikes of 1V. Both significant facilitating and depressing behaviors of this artificial synapse are observed with a relative amplitude of about 50% and a dynamic response <200ms. From a series of in-situ experiments, i.e. measuring the current–voltage characteristic curves in-situ and in real time, during the growth of the pentacene over a network of gold nanoparticles, we elucidate these results by analyzing the relationship between the organic film morphology and the transport properties. This synapstor works at a low energy of about 2nJ/spike. We discuss the implications of these results for the development of neuro-inspired computing architectures and interfacing with biological neurons.

Inductive crystallization effect of atomic-layer-deposited Hf0.5Zr0.5O2 films for ferroelectric application.

Ferroelectric HfxZr1-xO2 thin films are considered promising candidates for future lead-free CMOS-compatible ferroelectric memory application. The inductive crystallization behaviors and the ferroelectric performance of Hf0.5Zr0.5O2 thin films prepared by atomic layer deposition were investigated. Inductive crystallization can be induced by the film growth condition and appropriate top electrode selection. In this work, a Ni/Hf0.5Zr0.5O2/Ru/Si stack annealed at 550°C for 30 s in N2 ambient after the Ni top electrode has been deposited was manufactured, and it shows the best ferroelectric hysteresis loop in the dielectric thickness of 25 nm, with a remanent polarization value of 6 μC/cm2 and a coercive field strength of 2.4 MV/cm measured at 10 kHz. Endurance, retention, and domain switching current characteristics were evaluated well for potential application in the field of ferroelectric field effect transistor (FeFET) and nonvolatile ferroelectric memories (FeRAM).

Polymeric charge storage electrets for non-volatile organic field effect transistor memory devices

A review on polymeric charge storage electrets for constructing non-volatile organic field effect memory devices is presented.

Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-AuNPs) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-AuNP)n films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. For a single AuNP layer (i.e. PAD/TOA-AuNP)1) with a number density of 1.82 × 1012 cm−2, the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four AuNP layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔVth) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 106) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate.