Field-effect Transistor Memory Research Articles

High-Accuracy Deep Neural Networks Using a Contralateral-Gated Analog Synapse Composed of Ultrathin MoS₂ nFET and Nonvolatile Charge-Trap Memory

The development of high-accuracy analog synapse deep neural networks entails devising novel materials and innovative memory structures. We demonstrated an analog synapse with contralateral gates based on a two-dimensional (2D) field-effect transistor and nonvolatile charge-trap memory. Vertical integration of a MoS2-channel FET with a charge-trapping layer provided excellent charge controllability and gate-tunable nonvolatile storage. In the proposed contralateral-gate design, the read and write operations were separated to mitigate read disturb degradation. Reducing the MoS2channel thickness to the ultrathin scale allowed large threshold voltage shifts and on-resistance ( $\text{R}_{\text {ON}}$ ) modulations. This vertically integrated MoS2synapse device exhibited 55 conductance states, high conductance max–min ratio ( ${G}_{\text {MAX}}/ ~{G}_{\text {MIN}}$ ; ~50), low nonlinearity of $\alpha _{\text {p}}$ = −0.81 and $\alpha _{\text {d}}$ = −0.31, near ideal asymmetry of 0.5, and free of read disturb degradation. High neural network accuracy (>87%) is also obtained.

Nonvolatile and Neuromorphic Memory Devices Using Interfacial Traps in Two-Dimensional WSe2/MoTe2 Stack Channel.

Very recently, stacked two-dimensional materials have been studied, focusing on the van der Waals interaction at their stack junction interface. Here, we report field effect transistors (FETs) with stacked transition metal dichalcogenide (TMD) channels, where the heterojunction interface between two TMDs appears useful for nonvolatile or neuromorphic memory FETs. A few nanometer-thin WSe2 and MoTe2 flakes are vertically stacked on the gate dielectric, and bottom p-MoTe2 performs as a channel for hole transport. Interestingly, the WSe2/MoTe2 stack interface functions as a hole trapping site where traps behave in a nonvolatile manner, although trapping/detrapping can be controlled by gate voltage (VGS). Memory retention after high VGS pulse appears longer than 10000 s, and the Program/Erase ratio in a drain current is higher than 200. Moreover, the traps are delicately controllable even with small VGS, which indicates that a neuromorphic memory is also possible with our heterojunction stack FETs. Our stack channel FET demonstrates neuromorphic memory behavior of ∼94% recognition accuracy.

Complementary Type Ferroelectric Memory Transistor Circuits with P‐ and N‐Channel MoTe2

AbstractFerroelectric nonvolatile memory (FeNVM) field effect transistors (FETs) are reported using p‐channel MoTe2 and P(VDF‐TrFE) ferroelectric polymer, and furthermore a complementary type memory cell is demonstrated coupling p‐ and n‐channel MoTe2 FETs. A top‐gate p‐FET with P(VDF‐TrFE) and a bottom‐gate n‐FET with Al2O3 dielectric are integrated as one cell. Such a complementary type cell is more desirable research path in respect of power consumption but rare to find in 2D‐based memory reports. Among many 2D semiconductors MoTe2 is selected, because p‐type MoTe2‐based FeNVM is not reported yet, and also because it is relatively easy to obtain both p‐ and n‐channel from the homogeneous MoTe2. The integrated device also operates as a complementary metal oxide semiconductor inverter in a small voltage range from 0 to ≈2.5 V, but primarily works as a FeNVM circuit when p‐channel with top P(VDF‐TrFE) is biased with high voltages over the coercive electric field (Ec) of the polymer. The bottom gate n‐channel transistor operates as a switching device in the FeNVM cell, allowing voltage output signals during device operations. It is concluded that the complementary type FeNVM cell is practical and novel enough to report as a first time demonstration based on 2D MoTe2.

Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint

Compute-in-memory (CIM) is a promising computing paradigm to accelerate the inference of deep neural network (DNN) algorithms due to its high processing parallelism and energy efficiency. Prior CIM-based DNN accelerators mostly consider full custom design, which assumes that all the weights are stored on-chip. For lightweight smart edge devices, this assumption may not hold. In this article, CIM-based DNN accelerators are designed and benchmarked under different chip area constraints. First, a scheduling strategy and dataflow for DNN inference is investigated when only part of the weights can be stored on-chip. Two weight reload schemes are evaluated: 1) reload partial weights and reuse input/output feature maps and 2) load a batch of input and reuse the partial weights on-chip across the batch. Then, system-level performance benchmark is performed for the inference of ResNet-18 on ImageNet data set. The design tradeoffs with different area constraints, dataflow, and device technologies [static random access memory (SRAM) versus ferroelectric field-effect transistor (FeFET)] are discussed.

High-performance Nonvolatile Organic Photoelectronic Transistor Memory Based on Bulk Heterojunction Structure.

Depending on the storage mechanisms, organic field-effect transistor (OFET) memory is usually divided into floating gate memory, ferroelectric memory, and polymer-electret-based memory. In this work, a new type of nonvolatile OFET memory is proposed by simply blending a p-type semiconductor and a n-type semiconductor without using an extra trapping layer. The results show that the memory window can be effectively modulated by the dopant concentration of the n-type semiconductor. With the addition of a 5% n-type semiconductor, blending devices exhibit a large memory window up to 57.7 V, an ON/OFF current ratio (ION/IOFF) ≈ 105, and a charge retention time of over 10 years, which is comparable or even better than those of most of the traditional OFET memories. The discontinuous n-type semiconductor is set as a charge-trapping center for charge storage due to the quantum well-like organic heterojunctions. The generalization of this method is also investigated in other organic systems. Moreover, the blend devices are also applied to optical memory and show multilevel optical storage, which are further scaled up to 8 × 8 array to map up two-dimensional (2D) optical images with long-term retention and reprogramming characteristic. The results reveal that the novel system design has great potential application in the field of digital image memory and photoelectronic system.

Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory

We demonstrate novel analysis on electrical characteristics of ferroelectric-gate field effect transistor (FeFET), especially reverse DIBL (RDIBL) and negative differential resistance (NDR) phenomena through measurements of fabricated FeFETs and technology computer-aided design (TCAD) simulations. The FeFETs are embodied by extracting the ferroelectric properties using metal-ferroelectric-metal (MFM) capacitors and applying it to the gate stack of n-type FeFETs. Then, the device and the model parameters of the FeFETs are calibrated by matching TCAD simulation results to measured electrical characteristics. By the TCAD simulations which reflect the Preisach model considering multi-domain ferroelectric characteristics, it is revealed that RDIBL and NDR result from the local conduction band energy rising at the drain-side with drain voltage increasing. Furthermore, it is found that gate-induced drain leakage (GIDL) accelerates RDIBL with the help of the injection of the generated holes by GIDL in the floating body of FeFETs.

Organic Field-Effect Transistor Memory Device Based on an Integrated Carbon Quantum Dots/Polyvinyl Pyrrolidone Hybrid Nanolayer

In this work, we present a pentacene-based organic field-effect transistor memory (OFETM) device, which employs one-step microwave-assisted hydrothermal carbon quantum dots (CQDs) embedded in a polyvinyl pyrrolidone (PVP) matrix, to form an integrated hybrid nanolayer as the charge trapping layer. The as-prepared CQDs are quasi-spherical amorphous C, with sizes ranging from 5 to 20 nm, with a number of oxygen-containing groups and likely some graphite-like domains that produce CQDs with excellent electron-withdrawing characteristics. The incorporation of CQDs into PVP dielectric materials results in a bidirectional storage property. By optimizing the concentration of CQDs embedded into the PVP matrix, the OFETM shows excellent memory characteristics with a large memory window of 8.41 V under a programming/erasing (P/E) voltage of ± 60 V and a retention time of up to 104 s.

A simulation study on low voltage operability of hafnium oxide based ferroelectric FET memories

Lower limit of operable voltage for ferroelectric field effect transistor memories using hafnium oxide based ferroelectric gate dielectrics was estimated using circuit simulations. Assuming realistic array architecture, memory weakening by disturbs and restrictions set by sneak current were taken into account. For modeling ferroelectricity, a continuous Preisach model of hysteresis was used. The results show that the lowest possible operation voltage, not including variability and reliability margin, will be around ±2 V. It was found that moderate reduction of remanent polarization is beneficial for lowering both operation voltage and interfacial layer electric field stress.

Ferroelectric memory field-effect transistors using CVD monolayer MoS2 as resistive switching channel

Ferroelectric field-effect transistors (FeFETs) have been considered as promising electrically switchable nonvolatile data storage elements due to their fast switching speed, programmable conductance, and high dynamic range for neuromorphic applications. Meanwhile, FeFETs can be aggressively shrunk to the atomic scale for a high density device integration, ideally, without comprising the performance by introducing two-dimensional (2D) materials. So far, the demonstrated 2D material-based FeFETs mainly rely on mechanically exfoliated flakes, which are not favorable for large-scale industrial applications, and FeFETs based on organic ferroelectrics typically show a large writing voltage (e.g., >±20 V), making these types of memory devices impractical to be commercially viable. Here, we demonstrate that monolayer MoS2 grown by chemical vapor deposition (CVD) can be used as a resistive switching channel to fabricate FeFETs, in which the MoS2 channel is modulated by a hybrid gate stack of HfO2/ferroelectric HfZrOx thin films. The programming processes in the 2D MoS2 FeFETs originate from the ferroelectric polarization switching, yielding two distinct write and erase states for data storage and cumulative channel conductance for artificial synapse applications. Our 2D FeFETs show a low-voltage-driven feature (<±3 V) and gate-tunable ferroelectric hysteresis characteristics. The thin HfO2 layer in the hybrid gate stack likely plays crucial roles in preserving the ferroelectricity of the device and lowering the threshold of switching voltages through energy redistribution. Our findings open an avenue for the use of CVD-grown layered materials as the resistive switching mediums combined with HfO2-based ferroelectrics for future energy-efficient “brain-on-a-chip” hardware.

Donor-Acceptor Effect of Carbazole-Based Conjugated Polymer Electrets on Photoresponsive Flash Organic Field-Effect Transistor Memories.

The molecular structure of polymer electrets is crucial for creating diverse functionalities of organic field-effect transistor (OFET) devices. Herein, a conceptual framework has been applied in this study to design the highly photoresponsive carbazole-based copolymer electret materials for the application of photoresponsive OFET memory. As an electret layer, two 1,8-carbazole-based copolymers were utilized; the copoly(CT) consisted of carbazole as the donor group and thiophene as the π-spacer, whereas the copoly(CBT) was further introduced as an acceptor moiety, benzothiadiazole, for comparison. Both copolymers exhibited efficient visible-light absorption and photoluminescence quenching in the film state, indicating the formation of a considerable number of nonemissive excitons, one of the crucial factors for achieving photoinduced recovery behavior in OFET memories. Compared to copoly(CT) with the pure donor system, faster and more effective photoinduced recovery behavior was discovered in the copoly(CBT) with the conjugated donor-acceptor structure because of the coexistence of the conjugated donor and acceptor groups. Thus, the dissociation of the generated excitons facilitated the stimulating of the unique ambipolar trapping property, resulting in the high-density data storage devices with multilevel current states. In addition, the nonvolatile and durable characteristics demonstrated the feasibility in application of memory and photorecorders.

Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

Single-event-upset effect simulation of HfO<sub>2</sub>-based ferroelectric field effect transistor read and write circuits

Ferroelectric field effect transistor (FeFET) is a promising memory cell for space application. The FeFET can achieve non-destructive reading, and has the advantages of simple structure and high integration. Ferroelectric thin film’s size effect, retention performance and radiation resistance of ferroelectric thin films directly determine the performances of FeFET devices. The HfO<sub>2</sub> is widely used as a dielectric in complementary metal oxide semiconductor (CMOS) device and can solve the common integration problems for ferroelectric materials due to its CMOS compatibility. When the HfO<sub>2</sub>-based FeFETs are applied to aerospace electronics, the effects of various radiation particles need to be considered. The HfO<sub>2</sub>-based FeFET memory is still in the experimental stage, and there are no products of HfO<sub>2</sub>-based FeFET chips available from the market, so it is difficult to carry out experimental research on its single particle effect In the case of lacking the finished products of HfO<sub>2</sub>-based FeFET devices, using the device-hybrid simulation method to study the HfO<sub>2</sub>-based FeFET single-particle effect is a necessary and feasible content for the research on HfO<sub>2</sub>-based FeFET single-particle effects. In this paper, the device-circuit simulation method is used to build a read-write circuit of HfO<sub>2</sub>-based ferroelectric field-effect transistor. The change of read and write data after a single particle is incident on a ferroelectric field effect transistor memory cell and a sensitive node of a peripheral sense amplifier is studied, and the internal mechanism of read and write data fluctuation is analyzed. The results show that when high-energy particles enter into the drain of the ferroelectric memory cell in the read-write circuit, the memory cells in the “0” state generate electron-hole pairs, which accumulate inside the device, causing the gate electric field strength and ferroelectricity to increase, and the memory cell in the “1” state has a large fluctuation in the output transient pulse voltage signal due to the charge injection of the source, indicating that the ferroelectric memory cell has a good performance against particle flipping; when high-energy particles enter into the amplifier’s sensitive node, a collection current is generated, causing the amplifier in the state of reading “0” to turn on, and the output data to fluctuate. Owing to the fluctuation time being only 0.4 ns, the data does not have single-particle flipping energy under normal readout, and the HfO<sub>2</sub>-based FeFET read-write circuit has excellent resistance to single particles. When two beams of high-energy particles act on the drain of a ferroelectric memory cell successively in a time interval of 0.5 ns, the output data signal fluctuates more than in the case of a single beam of high-energy particles, and the final output voltage difference in the reading and writing “1” state becomes smaller.

Polymer field-effect transistor memory based on a ferroelectric nylon gate insulator

Ultra-smooth thin-films of nylons, one of the most successful commercialized polymers, have been realized for the application in ferroelectric field effect transistors.

Electron trapping mechanism in a multi-level organic fet memory using lithium-ion-encapsulated fullerene as the floating gate

We report on the electron trapping mechanism in a multi-level organic field effect transistor (OFET) memory using Lithium-ion-encapsulated fullerene (Li+@C60) as the floating gate. Based on the estimation of trapped electron number per each Li+@C60 molecule when a programming voltage was applied, the active domain of the floating gate was determined to be the surface of the Li+@C60 domain. An analysis of the cyclic voltammetry indicated that each Li+@C60 molecule can trap electrons at the trapping energy level of -4.94 and -4.49 eV. The number of trapped electron was confirmed by the ultraviolet-visible spectroscopy (UV-Vis).

Electron trapping mechanism in a multi-level organic fet memory using lithium-ion-encapsulated fullerene as the floating gate

We report on the electron trapping mechanism in a multi-level organic field effect transistor (OFET) memory using Lithium-ion-encapsulated fullerene (Li+@C60) as the floating gate. Based on the estimation of trapped electron number per each Li+@C60 molecule when a programming voltage was applied, the active domain of the floating gate was determined to be the surface of the Li+@C60 domain. An analysis of the cyclic voltammetry indicated that each Li+@C60 molecule can trap electrons at the trapping energy level of -4.94 and -4.49 eV. The number of trapped electron was confirmed by the ultraviolet-visible spectroscopy (UV-Vis).

Voltage-Controlled Magnonic Spin Tunneling Junction

We theoretically investigate the effective exchange interaction, $J_\mathrm{eff}$, mediated by conductive electrons within a nonmagnetic metal spacer, in the presence of a bias voltage, sandwiched by two ferromagnetic insulators. On the basis of the tight-binding model, we show the voltage and spacer thickness dependences of $J_\mathrm{eff}$, and its contorollability is demonstrated. We also propose a new magnonic device with the functions of both field effect transistor and non-volatile memory.

Multilevel Photonic Transistor Memory Devices Using Conjugated/Insulated Polymer Blend Electrets.

Photonic data storage has diverse optoelectronic applications such as optical sensing and recording, integrated image circuits, and multibit-storage flash memory. In this study, we employ conjugated/insulated polymer blends as the charge storage electret for photonic field-effect transistor memory devices by exploring the blend composition, energy level alignment, and morphology on the memory characteristics. The studied conjugated polymers included poly(9,9-di-n-octylfluorenyl-2,7-diyl) (PF), poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene] (MEH-PPV), poly[{2,5-di(3',7'-dimethyloctyloxy)-1,4-phenylene-vinylene}-co-{3-(4'-(3″,7″-dimethyloctyloxy)phenyl)-1,4-phenylenevinylene}-co-{3-(3'-(3',7'-dimethyloctyloxy)phenyl)-1,4-phenylenevinylene}] (SY-PPV), and poly[(9,9-di-n-octylfluorenyl-2,7-diyl)-alt-(benzo[2,1,3]thiadiazol-4,8-diyl)] (F8BT), and the insulated polymers were polystyrene (PS) and poly(methyl methacrylate) (PMMA). The photonic memory device using the PF/PS blend electret exhibited a dynamic switching behavior with light-writing and voltage-erasing processes both within only 1 s, along with a high contrast on the current on/off ratio between "Photo-On" and "Electrical-OFF" over 106 and the decent retention time for more than 3 months. In addition, the multilevel memory behavior could be observed using different light sources of 405, 450, and 520 nm or energy intensity, which was supported by surface potential analysis. The characteristics were superior to those of the devices using PF/PMMA blend due to the higher charge storage behavior of PS supported by fluorescence analysis. The PF/PS blend film prepared from the chlorobenzene solvent exhibited mesh-like and aggregated PF domains in the PS matrix and enhanced the contact surface area between the semiconductor and blend electret, leading to a higher memory window. The photonic memory behavior was also observed in the blend electrets of PS with the low band gap polymer, MEH-PPV, SY-PPV, or F8BT, by changing the photoresponsive light sources. Our study demonstrated a new electret system to apply on the multilevel photonic memory devices.

Filter-Free Selective Light Monitoring by Organic Field-Effect Transistor Memories with a Tunable Blend Charge-Trapping Layer.

Integration of selective photodetection and signal storage in a single device, such as organic field-effect transistor (OFET) memories, meets the demands for radiation monitoring and protection. A new strategy is developed to achieve filter-free and selective light monitoring by adopting a solution-processed blend charge-trapping layer in OFET memories, where the charge-trapping layer is composed of phenyl-C61-butyric acid methyl ester (PCBM) dispersed in a polymer electret thin film. The OFET memory without PCBM shows response only to ultraviolet light, whereas the spectral response edges are extended to the visible and near-infrared regions in the corresponding devices with relatively low and high contents of PCBM in the charge-trapping layer, respectively. A set of OFET memories with different PCBM contents is used to qualitatively evaluate the light composition in an optical source. The tunable spectral response in the OFET memories is ascribed to the additional photoassisted charge-trapping paths depending on the blend ratio in the charge-trapping layer. This mechanism may inspire alternative approaches to organic-based optical sensing and monitoring in flexible and wearable electronics.

Visible-blind UV monitoring with a photochromic charge trapping layer in organic field-effect transistors

An alternative strategy is proposed to achieve visible-blind ultraviolet (UV) monitoring. By introducing photochromic spiropyran (SP) molecules into the dielectric as the charge trapping layer, organic field-effect transistor (OFET) memories show a selective response to UV light and are inert to visible light. The photoisomerization of SP from the ring-close to ring-open states under UV illumination modifies its electronic structure, which facilitates electron trapping into the charge trapping layer and accordingly induces the memory effect. UV exposure recording can be realized by cumulative and nonvolatile electron trapping, enabling potential applications of OFET memories for UV monitoring in wearable electronics.

Multi-level operation of three-dimensionally stacked non-volatile ferroelectric polymer memory with high-performance hole-injection layer

Abstract Carrier injection from the source electrode to the semiconducting channel in a field-effect transistor (FET) is efficiently enhanced by inserting an interlayer capable of reducing the injection barrier, yielding a device with a greatly increased ON current. In this study, we demonstrated a non-volatile vertical-channel (VC) ferroelectric field effect transistor (FeFET) memory based on ferroelectric polarization switching of a ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as a gate insulator with a thin MoO3 interlayer. Owing to the facile hole injection through the MoO3 interlayer to a semiconducting channel of the FeFET, the saturated ON current was significantly increased, giving rise to a large ON/OFF memory margin. Optimization of the VC-FeFET thus led to a non-volatile memory operating at a programming voltage of ±25 V with a maximum ON/OFF current margin of 103, reliable time-dependent data retention for more than 1 year, and write/erase endurance for 105 cycles. Furthermore, by sequentially stacking three arrays of VC-FeFETs with the hole-injection interlayers, we fabricated three-dimensionally (3D) stacked VC-FeFETs. Each device had a sufficient ON/OFF current ratio for multi-level memory operation, in which four distinct states were repetitively programmed and erased with long-term data retention and reliable cycle endurance.