Ferroelectric-gate Field-effect Transistors Research Articles

Impact of ambient moisture on gate controllability in ferroelectric-gate field-effect transistors with bottom-gate geometry

Ferroelectric-gate field-effect transistors (FeFETs) with a bottom-gate geometry consisting of a ferroelectric HfO2 gate and an oxide channel have been intensively studied in recent years. However, there has been no detailed investigation into the impact of atmospheric exposure on device performance, even though the channel is often exposed to ambient air for process simplification, especially at the research stage. In this study, the ambient stability of an indium tin oxide channel FeFET with a ferroelectric Ce-HfO2 bottom gate was investigated. We found that ambient degradation of the gate controllability was caused by an increase in physisorbed water in the device owing to the intrusion of moisture. Mobile ions, such as H+, which can easily move through a network of hydrogen bonds formed by adjacent physisorbed water, may compensate for ferroelectric polarization. Finally, we demonstrated that the observed degradation can be managed effectively without compromising the original device characteristics using Al2O3 passivation gently formed via plasma-free deposition.

TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

An Extended Kolmogorov-Avrami-Ishibashi (EKAI) Model to Simulate Dynamic Characteristics of Polycrystalline-Ferroelectric-Gate Field-Effect Transistors.

A physics-based model on polarization switching in ferroelectric polycrystalline films is proposed. The calculation results by the model agree well with experimental results regarding dynamic operations of ferroelectric-gate field-effect transistors (FeFETs). In the model, an angle θ for each grain in the ferroelectric polycrystal is defined, where θ is the angle between the spontaneous polarization and the film normal direction. Under a constant electric field for a single-crystal film with θ = 0, phenomena regarding polarization domain nucleation and wall propagation are well described by the Kolmogorov-Avrami-Ishibashi theory. Since the electric fields are time-dependent in FeFET operations and the θ values are distributed in the polycrystalline film, the model in this paper forms an extended Kolmogorov-Avrami-Ishibashi (EKAI) model. Under a low electric field, the nucleation and domain propagation proceed according to thermally activated processes, meaning that switching the time scale of a grain with the angle θ is proportional to an exponential form as exp(const./Ezcosθ) [Ez: the film-normal electric field]. Wide θ distribution makes the time response quite broad even on the logarithmic scale, which relates well with the broad switching time experimentally shown by FeFETs. The EKAI model is physics based and need not assume non-physical distribution functions in it.

Demonstration of Ferroelectric-Gate Field-Effect Transistors With Recessed Channels

Demonstration of Ferroelectric-Gate Field-Effect Transistors With Recessed Channels

Ferroelectric-gate tunnel field-effect transistor one-transistor ternary contents addressable memory

In the era of ‘big data’, the von Neumann architecture has significant energy consumption and latency penalties for data transfer between memory and processor. However, ternary content addressable memories (TCAMs) enable fast and energy-efficient operation by performing a parallel search for given data and returning information about whether it matches. In this study, a single transistor (1T) ferroelectric-gate tunnel FET (FeTFET) was introduced for TCAM operations, and its functionality was verified through technology computer-aided design (TCAD) simulations. The FeTFET has intrinsic directional currents due to its unique p–i–n structure. Also, the transfer curve of the FeTFET can be shifted in both directions depending on the polarization state of the ferroelectric material. By combining these properties of the FeTFET, it was confirmed that stable search operations can be performed for stored logic states. Thus, compared to conventional TCAM cell that use two or more transistors, it is expected that the proposed 1T-TCAM cell can store and search more bits in the same area.

Effect of Hf x Zr1−x O2/Ge metal–ferroelectrics–insulator–semiconductor interfaces on polarization reversal behavior

To evaluate the polarization characteristics of ferroelectric-gate field-effect transistors, metal–ferroelectrics–insulator–semiconductor (MFIS) structures are often used. This study examines the influence of interface characteristics on polarization characterization in MFIS on low-impurity-concentration substrates by experimentally evaluating the ferroelectric properties of Hf x Zr1−x O2 (HZO)/Ge MFIS capacitors with different interface properties. Usually, polarization reversal behavior is not observed for MFIS capacitors on low-impurity-concentration substrates. However, it is found that, when the interface properties are poor and the interface state density is high, polarization reversal behavior can be observed even on the low-impurity concentration substrates. In lightly-doped MFIS capacitors with many interface states, the response of the interface states at low measurement frequencies suppresses the depletion layer change and voltage drop in the Ge substrate, resulting in the high electric field across the HZO films and observation of polarization reversal behavior.

Ferroelectric-gated variable-area capacitors with large capacitance tuning ratio using Ce-doped HfO2 film for both gate insulator and capacitor layer

We demonstrate a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a ferroelectric capacitor. A FeFET using an indium tin oxide (ITO) channel and a ferroelectric Hf0.86Ce0.14O2 gate insulator was fabricated by chemical solution deposition. The fabricated FeFET exhibited a high on-current of ∼0.18 mA μm−1 and a large on-/off-current ratio of 106. The large charge controllability of the FeFET allows the conductive ITO channel to act as an electrode switch that connects and disconnects two capacitors. In order to increase the capacitance density and the capacitance tuning ratio (CTR), we propose a structure wherein a 25-nm-thick ferroelectric film is applied as both a gate insulator and a capacitor. The proposed structure exhibited a large capacitance density of 12.5 nF mm−2 and a wide CTR of approximately 10 000. This work facilitates future integration of passive and active components for advanced highly efficient and miniaturized electronics.

Variable-area capacitors controlled by HfO2-based ferroelectric-gate field-effect transistors

We propose a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a paraelectric thin-film capacitor. Owing to the large charge controllability and nonvolatile memory function of the ferroelectric Hf0.86Ce0.14O2 (14% Ce-HfO2) gate insulator, the variable-area capacitors exhibited high capacitance tuning ratios of up to 184 with steep modulation to gate voltage swing (440 mV/decade), a capacitance-switching speed of less than 10 ms, and capacitance-memory-retention characteristics of up to 105 s. An FeFET with an indium tin oxide (ITO) channel and a ferroelectric 14% Ce-HfO2 gate insulator was fabricated as a switching FET via chemical solution deposition, followed by stacking a sputtered Al2O3 film as a variable capacitor. The fabricated FeFETs exhibited a high on-current of ∼0.15 A/mm, a large on/off current ratio of 107, a field-effect mobility of 15.6 cm2/V s, and a memory window of ∼5 V. The high on-current, i.e., low on-resistance (84 Ω), and the large on/off current ratio allow the ITO channel to act as a wiring that connects and disconnects two capacitors with different electrode areas; therefore, the proposed variable capacitor can achieve wide and steep modulation by ferroelectric gating. This study provides prospects for the future integration of passive and active components for advanced high-efficiency and miniaturized electronics such as power devices and communication equipment.

Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory

In this article, the interface trap-assisted ferroelectric polarization in ferroelectric-gate field effect transistors (FeFETs) is investigated based on technology computer-aided design (TCAD) simulations. The metal–ferroelectric–metal (MFM) capacitors and FeFETs are fabricated to reflect ferroelectric and device model parameters to the simulations. By introducing interface traps between ferroelectric layer and Interlayer (FE/IL) and implementing the charge trapping through nonlocal tunneling model, it is revealed that the trapped charges at the FE/IL interface enhance the polarization of the FE, and they determine a memory window (MW) by the compensation between the polarization enhancement and the trapping-induced threshold voltage shift. Furthermore, the effects of the remaining trapped charges depending on a trap relaxation on the MW are rigorously analyzed by monitoring the transient changes of the polarization and the trapped charges in pulse program/read operations.

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> ) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> scaling mitigate the σMW degradation.

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the 1T1C based ferroelectric random-access memory (FeRAM) and the 1T based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of HfO2 based ferroelectrics has turned out to be a game changer, as high- quality and scalable ferroelectric capacitors have since been reported [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 (HZO) system has attracted extra attention because of its wide composition range and relatively low processing temperature for the formation of the ferroelectric phase (o-phase), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed HZO-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers [2]. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers will all be presented and discussed, along with their potential for automotive applications at elevated temperatures. Furthermore, we proposed and demonstrated a novel 6T/4C dual-storage-port NVSRAM by integrating two pairs of HZO-based ferroelectric capacitors onto SRAM cells through the BEOL process, which is promising for numerous IoT applications [3].More coverage of this talk will focus on FeFET cells made by the same foundry using their conventional front-end CMOS process, except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize, primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [4,5]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [6,7]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [4]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [8]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [9]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology. The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [10]. This patented 3D memory technology will also be briefly discussed.[1] T. Mikolajick et al.,MRS Bulletin 43 340(2018) [2] H. Jiang et al., IMW2020 [3] H. Jiang et al., JEDS 8 935(2020) [4] T. P .Ma et al., IEEE EDL 23 386(2002) [5] X. Pan et al., Appl. Phys. Lett. 99 01305 (2011) [6] J.-P. Han et al., Integr. Ferroelect. 27 1053 (1999) [7] K.-H. Kim et al., IEEE EDL 23 82 (2002) [8] N. Gong et al., IEEE EDL 37 (9) 1123 (2016) [9] N. Gong et al., IEEE EDL 39 (1) 15 (2017). [10] Xiao Sun et al., U.S. Patent No. 9,818,848(2017)

Area-Scalable 109-Cycle-High-Endurance FeFET of Strontium Bismuth Tantalate Using a Dummy-Gate Process.

Strontium bismuth tantalate (SBT) ferroelectric-gate field-effect transistors (FeFETs) with channel lengths of 85 nm were fabricated by a replacement-gate process. They had metal/ferroelectric/insulator/semiconductor stacked-gate structures of Ir/SBT/HfO2/Si. In the fabrication process, we prepared dummy-gate transistor patterns and then replaced the dummy substances with an SBT precursor. After forming Ir gate electrodes on the SBT, the whole gate stacks were annealed for SBT crystallization. Nonvolatility was confirmed by long stable data retention measured for 105 s. High erase-and-program endurance of the FeFETs was demonstrated for up to 109 cycles. By the new process proposed in this work, SBT-FeFETs acquire good channel-area scalability in geometry along with lithography ability.

Artificially Intelligent Tactile Ferroelectric Skin.

Lightweight and flexible tactile learning machines can simultaneously detect, synaptically memorize, and subsequently learn from external stimuli acquired from the skin. This type of technology holds great interest due to its potential applications in emerging wearable and human‐interactive artificially intelligent neuromorphic electronics. In this study, an integrated artificially intelligent tactile learning electronic skin (e‐skin) based on arrays of ferroelectric‐gate field‐effect transistors with dome‐shape tactile top‐gates, which can simultaneously sense and learn from a variety of tactile information, is introduced. To test the e‐skin, tactile pressure is applied to a dome‐shaped top‐gate that measures ferroelectric remnant polarization in a gate insulator. This results in analog conductance modulation that is dependent upon both the number and magnitude of input pressure‐spikes, thus mimicking diverse tactile and essential synaptic functions. Specifically, the device exhibits excellent cycling stability between long‐term potentiation and depression over the course of 10 000 continuous input pulses. Additionally, it has a low variability of only 3.18%, resulting in high‐performance and robust tactile perception learning. The 4 × 4 device array is also able to recognize different handwritten patterns using 2‐dimensional spatial learning and recognition, and this is successfully demonstrated with a high degree accuracy of 99.66%, even after considering 10% noise.

Ferroelectric-Gate Field-Effect Transistor Memory With Recessed Channel

We demonstrate a novel ferroelectric-gate field effect transistor with recessed channel (R-FeFET) to improve memory window (MW), program/erase speed, long-time retention, and endurance simultaneously. Based on technology computer-aided design (TCAD) simulations including calibrated ferroelectric material (FE) parameters, it is revealed that the polarization is enhanced by the larger electric field (e-field) across the FE compared to a conventional planar FeFET, resulting in the wider MW and the faster program/erase speed. Moreover, the endurance/retention of the R-FeFET is expected to be improved as the e-field across the SiO2 interlayer is significantly reduced.

Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (&gt; 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.

Device-design optimization of ferroelectric-gated vertical tunnel field-effect transistor to suppress ambipolar current

Device-design optimization of a ferroelectric-gated vertical tunnel field-effect transistor (TFET) with a germanium source is performed using a technology computer-aided design simulation tool. In order to improve the device performance as well as to suppress the ambipolar current, the vertical length of the ferroelectric layer in the gate stack of the TFET is engineered. When the channel region is partially controlled with the ferroelectric layer, the device performance such as the on-state drive current and subthreshold swing (SS) can be improved (e.g. ∼ 3.08 × 10–4 A/μm, ∼ 3.28 × 1010, and a minimum SS of 22 mV/decade at 300 K). Moreover, the ambipolar current ( ∼ 21.6 pA/μm) is comparable to or even better than that of the conventional TFET.

Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory

We demonstrate novel analysis on electrical characteristics of ferroelectric-gate field effect transistor (FeFET), especially reverse DIBL (RDIBL) and negative differential resistance (NDR) phenomena through measurements of fabricated FeFETs and technology computer-aided design (TCAD) simulations. The FeFETs are embodied by extracting the ferroelectric properties using metal-ferroelectric-metal (MFM) capacitors and applying it to the gate stack of n-type FeFETs. Then, the device and the model parameters of the FeFETs are calibrated by matching TCAD simulation results to measured electrical characteristics. By the TCAD simulations which reflect the Preisach model considering multi-domain ferroelectric characteristics, it is revealed that RDIBL and NDR result from the local conduction band energy rising at the drain-side with drain voltage increasing. Furthermore, it is found that gate-induced drain leakage (GIDL) accelerates RDIBL with the help of the injection of the generated holes by GIDL in the floating body of FeFETs.

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the one-transistor-one-capacitor (1T1C) based ferroelectric random-access memory (FeRAM) and the single-transistor (1T) based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials (such as PZT and SBT) have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of hafnium oxide (HfO2)-based ferroelectrics has turned out to be a game changer, as high-quality and scalable ferroelectric capacitors have since been reported, including TiN/Al:HfO2/TiN-based 3D deep-trench capacitors [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 system has attracted extra attention because of its wide composition range and relatively low processing temperature (<= 400 0C), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed Hf0.5Zr0.5O2-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers have all been systematically characterized and will be discussed, as well as their potential for automotive applications at elevated temperatures.More coverage of this talk will be focused on FeFET cells made by the same foundry using their conventional front-end CMOS process except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [2,3]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [4,5]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [2]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [6]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [7]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology.The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND-Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [8]. This patented 3D memory technology will also be briefly discussed.This work was supported by the National Science Foundation (NSF) under Award No: 1609162.

Understanding of Polarization-Induced Threshold Voltage Shift in Ferroelectric-Gated Field Effect Transistor for Neuromorphic Applications

A ferroelectric-gated fin-shaped field effect transistor (Fe-FinFET) is fabricated by connecting a Pb(Zr0.2Ti0.8)O3-based ferroelectric capacitor into the gate electrode of FinFET. The ferroelectric capacitor shows coercive voltages of approximately −1.5 V and 2.25 V. The polarization-induced threshold voltage shift in the Fe-FinFET is investigated by regulating the gate voltage sweep range. When the maximum positive gate to source voltage is varied from 4 V to 2 V with a fixed starting negative gate to source voltage, the threshold voltage during the backward sweep is increased from approximately −0.60 V to 1.04 V. In the case of starting negative gate to source voltage variation from −4 V to −0.5 V with a fixed maximum positive gate to source voltage of 4 V, the threshold voltage during the forward sweep is decreased from 1.66 V to 0.87 V. Those results can be elucidated with polarization domain states. Lastly, it is observed that the threshold voltage is mostly increased/decreased when the positive/negative gate voltage sweep range is smaller/larger than the positive/negative coercive voltage, respectively.

A time-domain analog weighted-sum calculation circuit using ferroelectric-gate field-effect transistors for artificial intelligence processors

Time-domain analog computing with transient states (TACT) approaches have been proposed to realize high performance artificial intelligence (AI) processors, which have over 100 times higher energy efficiency than the latest digital AI processors. Such approaches require analog memory devices that can hold and control very high resistance on the order of giga-ohms to tera-ohms, with nonvolatility and rectification. Memory devices with a field-effect transistor (FET) structure can operate in a subthreshold region to realize such high resistance, and can also rectify the current using FET operation. In this paper, we propose using ferroelectric-gate FETs (FeFETs) as a candidate for such devices. We design crossbar circuit architectures for using them, and show measurement results for device characteristics as analog memory devices with pulse control based on TACT approaches, and evaluation results for weighted-sum calculation operation in proof-of-concept FeFET circuits.