Analysis on Reverse Drain-Induced Barrier Lowering and Negative Differential Resistance of Ferroelectric-Gate Field-Effect Transistor Memory

Abstract

We demonstrate novel analysis on electrical characteristics of ferroelectric-gate field effect transistor (FeFET), especially reverse DIBL (RDIBL) and negative differential resistance (NDR) phenomena through measurements of fabricated FeFETs and technology computer-aided design (TCAD) simulations. The FeFETs are embodied by extracting the ferroelectric properties using metal-ferroelectric-metal (MFM) capacitors and applying it to the gate stack of n-type FeFETs. Then, the device and the model parameters of the FeFETs are calibrated by matching TCAD simulation results to measured electrical characteristics. By the TCAD simulations which reflect the Preisach model considering multi-domain ferroelectric characteristics, it is revealed that RDIBL and NDR result from the local conduction band energy rising at the drain-side with drain voltage increasing. Furthermore, it is found that gate-induced drain leakage (GIDL) accelerates RDIBL with the help of the injection of the generated holes by GIDL in the floating body of FeFETs.