Comprehensive TCAD-Based Validation of Interface Trap-Assisted Ferroelectric Polarization in Ferroelectric-Gate Field-Effect Transistor Memory

Abstract

In this article, the interface trap-assisted ferroelectric polarization in ferroelectric-gate field effect transistors (FeFETs) is investigated based on technology computer-aided design (TCAD) simulations. The metal–ferroelectric–metal (MFM) capacitors and FeFETs are fabricated to reflect ferroelectric and device model parameters to the simulations. By introducing interface traps between ferroelectric layer and Interlayer (FE/IL) and implementing the charge trapping through nonlocal tunneling model, it is revealed that the trapped charges at the FE/IL interface enhance the polarization of the FE, and they determine a memory window (MW) by the compensation between the polarization enhancement and the trapping-induced threshold voltage shift. Furthermore, the effects of the remaining trapped charges depending on a trap relaxation on the MW are rigorously analyzed by monitoring the transient changes of the polarization and the trapped charges in pulse program/read operations.