Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

Kitae Lee,Byung-Gook Park,Sihyun Kim,Daewoong Kwon

doi:10.3390/app10144977

Kitae Lee, Byung-Gook Park + Show 2 more

Open Access

https://doi.org/10.3390/app10144977

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Journal: Applied sciences	Publication Date: Jul 20, 2020
Citations: 2	License type: CC BY 4.0

Affiliation: Seoul National University, Inha University

Abstract

Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.

Highlights

Tunneling-based ternary complementary metal-oxide-semiconductor (TCMOS) technology has been reported recently [1,2,3]
Before identifying the operations of TCMOS, the electrical characteristics of TNMOS
The IOFF is band-to-band tunneling (BTBT) at the drain-side tunnel junction and the IOFF increases with the larger VD (Figure 3)

Summary

Introduction

Tunneling-based ternary complementary metal-oxide-semiconductor (TCMOS) technology has been reported recently [1,2,3]. Instead of the binary systems of the existing complementary metal-oxide-semiconductor (CMOS) technology, the third output voltage (Vout ) state is formed in the ternary systems, and it has been spotlighted in terms of scaling and energy-efficiency [4,5]. In the TCMOS, the off-current (IOFF ) levels of NMOS (n-type MOS) and PMOS (p-type MOS), which are generated by band-to-band tunneling (BTBT), should be matched to form the third Vout state during inverter operations. FE-TCMOS, technology computer-aided design (TCAD) simulations with the calibrated ferroelectric material parameters used and thetoternary operations are rigorously compared between. FE-TCMOS, technology computer-aided design (TCAD) simulations with the calibrated ferroelectric material parameters are used and the ternary operations are rigorously compared between TCMOS. To embody the ferroelectricity in FE-TCMOS (Figure 1a,b), a metal-ferroelectric-metal (MFM)

Experiments andfabricated

Tunneling-Based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor

Operation characteristics of FE-TCMOS

Conclusions