Ferroelectric-gate Field-effect Transistors Research Articles

Operational method of a ferroelectric (Fe)-NAND flash memory array

Operations of arrayed ferroelectric (Fe)-NAND flash memory cells: erase, program and read were demonstrated for the first time using a small cell array of four word lines by two NAND strings. The memory cells and select-gate transistors were all n-channel Pt/SrBi2Ta2O9/Hf-Al-O/Si ferroelectric-gate field effect transistors. The erase was performed by applying 10 µs wide 7 V pulses to n- and p-wells. The program was performed by applying 10 µs wide 7 V pulses to selected word lines. Accumulated read currents of 51 programmed patterns in the Fe-NAND flash memory cell array successfully showed distribution of the two distinguishable ‘0’ and ‘1’ states. The margin between the two states became wider by applying a verification technique in programming a cell out of the eight. Retention times of bit-line currents were obtained over 33 h for both the ‘0’ and ‘1’ states in a program pattern.

Ferroelectric Properties of BaZrO3 Doped Sr0.8Bi2.2Ta2O9 Thin Films

Novel sol–gel derived Sr0.8Bi2.2Ta2O9 (SBT) doped with 5 and 7% molar ratio BaZrO3 (BZ) thin films were fabricated, characterized, and electrical properties were evaluated with Pt electrodes. X-ray diffraction (XRD) analysis showed all the characteristic peaks of the layered perovskite structure with (115) orientation and slight peak broadening by BZ doping. X-ray photoelectron spectra (XPS) showed a small shift in the Sr 3d peak with BZ substitution. Scanning electron microscopy (SEM) cross-sectional photographs of the films show smaller grain size and greater porosity with BZ addition. The remanent polarization (2Pr) was significantly reduced from ∼16.4 µC/cm2 for SBT to ∼2.3 µC/cm2 for SBT with 7% BZ. Capacitance–voltage measurements performed at a frequency of 1 MHz showed butterfly type hysteresis loops, which is further evidence of ferroelectricity of the modified SBT, and dielectric constant of 135 for SBT with 7% BZ. Leakage current measurements showed one order of magnitude higher leakage current for SBT with 5% BZ compared to SBT. Lower film dielectric constant leads to higher leakage current in BZ doped SBT. Although leakage mechanisms predict this general trend, it runs counter to the objective of preparing ferroelectric films with low leakage and low dielectric constants for ferroelectric gate field-effect transistor (FeFET) type memory.

Toward a low-voltage multiferroic transistor: Magnetic (Ga,Mn)As under ferroelectric control

The persistent field effect control of ferromagnetism in a diluted magnetic semiconductor by low-voltage polarizing pulses is demonstrated in a ferroelectric gate field effect transistor configuration. The Curie temperature of the (Ga,Mn)As channel is unambiguously signaled by a cusp in the temperature derivative of resistance. Polarization reversal in the ferroelectric copolymer polyvinylidene fluoride with trifluoroethylene P(VDF-TrFE) by voltage pulses of less than 10 V results in a reproducible nonvolatile shift in the cusp by as much as 7%–9%. The unique combination of a relatively large spontaneous polarization and low dielectric constant of the P(VDF-TrFE) gate promises a further reduction in the operation voltage.

Threshold voltage adjustment of ferroelectric-gate field effect transistors by ion implantation

The electric properties of ferroelectric-gate field-effect transistors (FeFETs) are investigated by using ion implantation. The doping concentration increases from 4 × 1014 to 1 × 1018 cm−3, and the corresponding threshold voltages of the FeFETs shift from 0.18 to −1.65 V, and from 0.98 to −0.54 V for the left- and right-side threshold voltages, respectively, which can be fitted to a theoretical result. The retention is measured at different doping concentrations for about 2 days, and all exhibit good retention characteristic. The results show that ion implantation is an effective method to adjust the threshold voltage in FeFET technology.

Characteristics of Au/SBT/LZO/Si MFIS structure for ferroelectric-gate field-effect transistors

Non-volatile memories using ferroelectric-gate field-effect transistors (Fe-FETs) with metal/ferroelectric/semiconductor gate stack (MFS-FETs) have superior advantages such as non-destructive read operation and high density. However, the interfacial reactions between ferroelectric materials and Si substrates make it difficult to obtain good electrical properties of MFS-FETs. As an alternative solution, Fe-FETs with a metal/ferroelectric/insulator/insulator/semiconductor gate stack (MFIS-FETs) have been proposed. We prepared SrBi2Ta2O9 (SBT) film as a ferroelectric layer and LaZrOx (LZO) film as the insulating buffer layer, and then fabricated the n-channel Fe-FETs with the Au/SBT/LZO/Si structure. The thickness of the LZO buffer layer and SBT film deposited by a sol-gel method were about 35 nm and 450 nm, respectively. From the electrical properties of the LZO film on Si, no hysteresis was observed in the C-V curve and the leakage current density was about 1.4 × 10-7 A/cm2 at 5 V. SBT film on the LZO/Si structure was crystallized in a polycrystalline phase with a highly preferred (115) orientation. The C-V characteristics of Au/SBT/LZO/Si structure showed a clockwise hysteresis loop and the memory window width increased as the bias voltage increased. The fabricated Fe-FETs showed typical n-channel MFIS-FETs C-V characteristics and the current on/off ratio was about 103. Also, the memory window width was about 0.7 V.

Electrical Characteristics of Controlled-Polarization-Type Ferroelectric-Gate Field-Effect Transistor

We propose a novel ferroelectric-gate field-effect transistor (FET) with a polar semiconductor channel, which is called a controlled-polarization-type ferroelectric-gate FET. The essential factor for this device is the stabilization of the spontaneous polarization of the ferroelectric film by the spontaneous polarization of a polar semiconductor, such as ZnO or GaN. We demonstrate two types of controlled-polarization-type ferroelectric-gate thin film transistors (TFTs), which are the ZnO/YMnO3/Pt bottom-gate-type structure and Pt/PZT/ZnO top-gate-type structure. Both structures show n-channel-type transistor operation with the memory effect originating from ferroelectricity. From the electrical characteristics of ferroelectric-gate TFTs, the effects of ferroelectricity, gate leakage current, space charge, and charge injection on the device operation are discussed.

Nondestructive Readout of Ferroelectric-Gate Field-Effect Transistor Memory With an Intermediate Electrode by Using an Improved Operation Method

We investigated the reading and writing of ferroelectric-gate field-effect transistor memory with an intermediate electrode (IF-FET) to achieve perfect nondestructive readouts. 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In order to solve this issue, a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> memory state was used instead of the previous <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> memory state. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sup> state was induced by applying a pulse combined with a positive voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) and a negative voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> ). <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> was to reset the previously written memory states, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> was to control the amount of remanent polarization. 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The appropriate heights of the writing and reading voltages were determined individually from the viewpoint of good nondestructive readout and large Delta <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">O</sub> . As a result, it was verified experimentally that the reading endurance reached more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> cycles and that the retention time of IF-FET at 150 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C was possible to exceed ten years.

A Ferroelectric Gate Field Effect Transistor with a ZnO/Pb(Zr,Ti)O3 Heterostructure Formed on a Silicon Substrate

We have developed a ferroelectric gate field effect transistor (FeFET) with a stacked oxide structure of ZnO/Pb(Zr,Ti)O3 (PZT)/SrRuO3 (SRO) on a Pt/SiO2-coated silicon substrate. The PZT film which acted as a ferroelectric gate insulator was completely oriented in the (111) direction. The well oriented PZT film was realized by the insertion of the SRO layer, which electrically acted, together with the bottom Pt layer as a bottom gate electrode. In order to realize a sharp heterointerface of ZnO/PZT, we applied chemical–mechanical-polishing (CMP) to the PZT surface giving rise to a minimized surface roughness of less than 0.65 nm (rms). The ZnO film stacked on the smooth PZT surface exhibited a c-axis orientation. Subsequently, the source and drain electrodes of Pt/Ti were formed on the ZnO surface. With a drain-to-source voltage of 0.1 V, the conduction current through the ZnO/PZT heterointerface was characterized. A large on/off current ratio (Ion/Ioff) higher than 105 was obtained between the gate voltage conditions of +10 and -10 V owing to the polarization reversal of the PZT gate. Notably, the on/off ratio was stable for more than 105 s without the application of gate bias.

Current status of ferroelectric-gate Si transistors and challenge to ferroelectric-gate CNT transistors

Current status of ferroelectric-gate FETs (field effect transistors) is reviewed. First, characteristics of Si FETs with MFIS (metal–ferroelectric–insulator–semiconductor) gate structures are discussed. It has been shown that the data retention characteristics of ferroelectric-gate FETs are much improved by use of HfO2-based buffer layers which are inserted between the ferroelectric-gate film and Si substrate for preventing inter-diffusion of constituent elements. Then, usefulness of organic ferroelectrics such as copolymers of vinyliden fluoride and trifluoroethylene (P(VDF–TrFE)) in fabrication of MFIS devices is demonstrated. In an Au/P(VDF–TrFE)/Ta2O5/Si MFIS diode, a memory window as wide as 2.9 V has been obtained with a voltage sweep of ±4 V. Finally, operation mechanisms in ferroelectric-gate CNT (carbon nano-tube) transistors are discussed, assuming Schottky barrier conduction at the source and drain contacts.

Inorganic and Organic Ferroelectric Thin Films for Memory Applications

Electrical properties of inorganic and organic ferroelectric thin films are discussed from viewpoints of ferroelectric random access memory (FeRAM) applications. It has been found in BiFeO3 films formed by chemical solution deposition that the leakage current at high electric field decreases significantly by substituting Mn atoms for Fe atoms. In these films, well saturated hysteresis loops in P-E (polarization vs. electric field) characteristics have been observed. It has also been found that co-substitution of La and Ni atoms to BiFeO3 films is effective to decrease the leakage current. Next, properties of organic ferroelectric thin films suitable for fabricating ferroelectric-gate FETs (field effect transistors) are discussed. It has been found in capacitors with a 60nm-thick P(VDF+TrFE) (polyvinyliden fluoride-trifluoroethylene) film that the remanent polarization is as large as 11.9 μC/cm2 and the coercive voltage is as low as 2 V.

Nonvolatile Memory Using Epitaxially Grown Composite-Oxide-Film Technology

We have developed a ferroelectric-gate field-effect transistor (FeFET) composed of heteroepitaxially stacked oxide materials. A semiconductor film of ZnO, a ferroelectric film of Pb(Zr,Ti)O3 (PZT), and a bottom gate electrode of SrRuO3 (SRO) are grown on a SrTiO3 (STO) substrate. Structural characterization shows a heteroepitaxy of the fabricated ZnO/PZT/SRO/STO structure with good crystalline quality and the absence of an interface reaction layer. When the polarization direction of the PZT film is downward, all the electrons across the ZnO film are depleted. When the polarization direction is upward, on the other hand, quasi-two-dimensional electron gas is accumulated at the ZnO/PZT interface. The switching of the quasi-two-dimensional electron gas between the two states is confirmed by capacitance–voltage measurements. Drain and source electrodes of Pt/Ti are formed on the ZnO film and in-plane conduction at the ZnO/PZT interface is probed. When gate voltages applied to the bottom electrode are swept between -10 and 10 V, the on/off ratio of drain currents is higher than 105. Such a high on/off ratio is preserved even after 105 s and the extrapolation of the retention behavior predicts a definite memory window of more than 10 years.

Threshold-voltage distribution of Pt/SrBi2Ta2O9/Hf–Al–O/Si MFIS FETs

Statistical distribution of the threshold voltage Vth for more than 90 Pt/SrBi2Ta2O9/Hf–Al–O/Si ferroelectric-gate field-effect transistors (FeFETs) is reported for both p- and n-channel devices. The average memory window is nearly 1.2 V at the sweep voltage amplitude of 5 V (between −4 V and 6 V for the p-channel, and ±5 V for the n-channel). The standard deviations of Vth are about 7–8% and 3–5% of the memory window for the p- and n-channel FeFETs, respectively. The result indicates a promising level of demonstrating a small-scale circuit by using this technology.

Fabrication and properties of silicon-based (Bi,Sm)4Ti3O12 thin film

Abstract Ferroelectric Bi 3.5 Sm 0.5 Ti 3 O 12 (BST) thin film has been grown on n-type Si (1 0 0) substrate by chemical solution deposition and spin coating technique. X-ray diffraction and atomic force microscope analyses confirmed that the film crystallized well at 700 °C. Metal-ferroelectric-semiconductor (MFS) configuration has been fabricated using BST as ferroelectric layer. The electrical measurements were conducted in MFS capacitor. The current–voltage characteristic displayed good insulating properties. Apparent counterclockwise hysteresis of capacitance–voltage curve for this film as the ferroelectric hysteresis was observed. The measurements of dielectric constant and dissipation factor as a function of frequency exhibited excellent dielectric properties. The MFS structure can be valuable for ferroelectric-gate field effect transistor.

FERROELECTRIC GATE FET MEMORY BASED ON CONDUCTION OF FERROELECTRIC-INSULATOR INTERFACE

ABSTRACT A new type of ferroelectric gate field effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between ferroelectric and insulator layers and needs no semiconductor. This FET consists of source and drain electrodes on ferroelectric film (Pb(Zr0.52Ti0.48)O3(PZT)) prepared on Pt/TiO2/SiO2/Si substrate, and gate electrode on HfO2 insulator film on the PZT film between the source and the drain electrodes. Drain current flows through the interface of the ferroelectric and the insulator. Drain current versus gate voltage characteristics shows clockwise hysteresis loop similarly to the conventional p-channel FET with ferroelectric gate. The FET shows that the On/Off ratio of the conduction current is about 105 and the Off state current is about 10− 10A.

Development of Microwave-Excited Plasma-Enhanced Metal–Organic Chemical Vapor Deposition System for Forming Ferroelectric Sr2(Ta1-x,Nbx)2O7 Thin Film on Amorphous SiO2

Sr2(Ta1-x,Nbx)2O7 (STN; x = 0.3) is suitable for use as ferroelectric gate field-effect transistors (FETs) for one-transistor-type ferroelectric memory devices, because it has a low dielectric constant. For applications using metal–ferroelectric–insulator–semiconductor (MFIS) FETs, crystallization of ferroelectric film on insulator is necessary. Perovskite STN can be successfully obtained on amorphous SiO2 by ferroelectric-multilayer-stack (FMLS) deposition, which uses alternating steps of STN sputtering deposition and oxygen radical treatment. In this study, we report on a newly developed microwave-excited plasma-enhanced metal–organic chemical vapor deposition (MOCVD) system, in which STN can be deposited in radical oxygen atmosphere. We succeeded in the fabrication of STN on amorphous SiO2 in a single process. The IrO2/STN (200 nm)/SiO2 (10 nm)/p-type Si device shows capacitance–voltage (C–V) hysteresis curves and a memory window of 1.2 V with a 5 V writing operation.

Technology of Ferroelectric Thin-Film Formation with Large Coercive Field on Amorphous SiO2 by Ion-Bombardment-Assisted Sputtering and Oxygen Radical Treatment for Future Scaling Down of Ferroelectric Gate Field-Effect Transistor Memory Device

Sr2(Ta1-x,Nbx)2O7 (perovskite STN; x=0.3) is one of the most practical candidates for one-transistor-type ferroelectric memory devices, because it has a low dielectric constant. However, in the application to metal–ferroelectric–insulator–Si field-effect transistor (MFIS-FET) memory devices, the fabrication of STN on an amorphous insulator, such as SiO2, is difficult. In particular, in the case of STN, because its crystallization annealing temperature is 950 °C, the metal elements of STN and Si react with each other during crystallization annealing. As a result, perovskite STN cannot be fabricated. To overcome this problem, we have developed an ion-bombardment-assisted sputtering method. Furthermore, to obtain universal conditions for forming perovskite STN based on plasma physics, plasma parameters such as ion bombardment energy and ion flux, were measured. Perovskite STN was obtained when the ion bombardment energy was 38 eV and the normalized Kr ion flux was 78 [ions/atom]. An IrO2/STN (140 nm)/STN seed layer (10 nm)/Si device whose STN was fabricated under these plasma conditions, shows square hysteresis curves and a memory window of 1.7 V under an 8 V writing operation. This value corresponds to a coercive field of 55 kV/cm.

Data Retention and Readout Degradation Properties of Pt/Sr0.7Sm0.07Bi2.2Ta2O9/HfO2/Si Structure Ferroelectric-Gate Field Effect Transistors

We discuss the data retention and readout degradation properties of ferroelectric-gate field-effect transistors (FeFETs) with Pt/Sr0.7Sm0.07Bi2.2Ta2O9/HfO2/Si structures. We first point out that to read out the stored data correctly, unselected FeFETs should be turned off during the readout process and that this process causes a significant reduction of ON readout current. We next characterize the data retention properties of Pt/Sr0.7Sm0.07Bi2.2Ta2O9/HfO2/Si structure n-channel FeFET by taking the readout process into account. It is shown that the retention property measured by applying positive readout pulses after holding at VG=0 V for 30 s, is similar to that measured by the conventional method in which drain current is continuously measured at a positive hold voltage.

Recent Progress in Ferroelectric Random Access Memory Technology

AbstractIn this paper, ferroelectric materials suitable for realizing high-density 1T1C-type (capacitor-type) FeRAM are first reviewed. It is found in BiFeO3(BFO) films formed by chemical solution deposition that leakage current density at a low electric field increases by substitution of Mn and Cr atoms for Fe atoms. But, it is also found that the breakdown characteristic is much improved by substitution of these atoms. Because of the better breakdown characteristic, the leakage current densities in the 3 and 5% Mn-substituted films are lower than that in an undoped BFO film at an applied electric field of 1MV/cm at room temperature, and thus well saturated hysteresis loops in P-E (polarization vs. electric field) characteristics are observed in these films.Next, recent technological progress in transistor-type FeRAM, in which data are stored in a single ferroelectric-gate FET(field effect transistor), is discussed. It is demonstrated that the data retention time of ferroelectric-gate FETs is much improved by use of HfO2-based buffer layers which are inserted between the ferroelectric film and Si substrate for preventing interdiffusion of constituent elements. Particular attention is paid to FETs with a Pt/SrBi2Ta2O9/HfO2/Si gate structure, in which the data retention time longer than 30 days has been attained. Finally, the cell structure and operation principle of 1T (one transistor)-type FeRAM are discussed.

Fabrication and Characterization of Ferroelectric Gate Field-Effect Transistor Memory Based on Ferroelectric–Insulator Interface Conduction

A new type of ferroelectric gate field-effect transistor (FET) using ferroelectric–insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and requires no semiconductor. The channel region of the FET is composed of a Pt/insulator HfO2/ferroelectric Pb(Zr0.52Ti0.48)O3 (PZT)/Pt/TiO2/SiO2/Si multilayer, and the source and drain areas are formed at the interface of the PZT and HfO2 films. Drain current versus gate voltage characteristics show a clockwise hysteresis loop similar to that for a conventional p-channel transistor. The FET shows that the on/off ratio of the conduction current is within 105 to 106 and that the off-state current is about 10-10 A.

Operation of Ferroelectric Gate Field-Effect Transistor Memory with Intermediate Electrode using Polycrystalline Capacitor and Metal–Oxide–Semiconductor Field-Effect Transistor

We have investigated the basic operation of a ferroelectric gate field-effect transistor (F-FET) memory with an intermediate electrode for data writing, using a discrete circuit which consists of a polycrystalline ferroelectric capacitor connected serially to the gate of a commercial n-channel metal–oxide–semiconductor (MOSFET). By sputtering, a ferroelectric capacitor Cf was formed as a (RuO2 top electrode)/poly-Pb(Zr0.52Ti0.48)O3(PZT)/(Pt/RuO2 bottom electrode) structure on a SiO2/Si substrate. The readout characteristics showed nondestructive operation. It was also shown that the output voltage for the positive and the negative polarization memory states corresponded very well with the intermediate electrode voltages on the gate of the MOSFET. Furthermore, the ratio of the ferroelectric capacitor to the input capacitor of the MOSFET was found to be an important factor influencing the cycle number of nondestructive reading and the difference in output voltage between the positive and negative polarization states.