Gate Feedback Research Articles

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Design and performance analysis of tri-layered strained Si/Si1–x Ge x /Si heterostructure DG feedback FET

This work presents the design and performance analysis of a tri-layered strained Si/Si1−x Ge x /Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain in the device by sandwiching a Si1−x Ge x layer between two thin Si layers to provide high ON current as well as ultra-steep switching characteristics. The device offers a significantly high ON current (3.4 x 10−3 A/μm), high I ON /I OFF ratio (∼1010), a large memory window of 1.06 V, and an extremely low subthreshold swing (∼0.3 μ V/decade), which can be very useful for memory and neuromorphic applications. Furthermore, the ON/OFF switching of the device has been accomplished at a lower threshold voltage (0.287 V), allowing it to be utilized in low-power electronics. Synopsys TCAD tool has been used to create the device structure and analyze the electrical performances of the device.

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3 × 10−4 A/μm) with a large I ON /I OFF ratio (3 × 1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS < 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−x Ge x ) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

Suppressed threshold voltage roll-off and ambipolar transport in multilayer transition metal dichalcogenide feed-back gate transistors

The layered semiconducting transition metal dichalcogenides (s-TMDs) have attracted considerable interest as the channel material for field-effect transistors (FETs). However, the multilayer s-TMD transistors usually exhibit considerable threshold voltage (Vth) shift and ambipolar behavior at high source-drain bias, which is undesirable for modern digital electronics. Here we report the design and fabrication of double feedback gate (FBG) transistors, i.e., source FBG (S-FBG) and drain FBG (D-FBG), to combat these challenges. The FBG transistors differ from normal transistors by including an extra feedback gate, which is directly connected to the source/drain electrodes by extending and overlapping the source/drain electrodes over the yttrium oxide dielectrics on s-TMDs. We show that the S-FBG transistors based on multilayer MoS2 exhibit nearly negligible Vth roll-off at large source-drain bias, and the D-FBG multilayer WSe2 transistors could be tailored into either n-type or p-type transport, depending on the polarity of the drain bias. The double FBG structure offers an effective strategy to tailor multilayer s-TMD transistors with suppressed Vth roll-off and ambipolar transport for high-performance and low-power logic applications.

Drain-engineered carbon-nanotube-film field-effect transistors with high performance and ultra-low current leakage

A small bandgap and light carrier effective mass (m0) lead to obvious ambipolar transport behavior in carbon nanotube (CNT) field-effect transistors (FETs), including a high off-state current and severe degradation of the subthreshold swing (SS) with increasing drain bias voltage. We demonstrate a drain-engineered method to cope with this common problem in CNT-film FETs with a sub-µm channel length, i.e., suppressing the ambipolar behavior while maintaining high on-state performance by adopting a feedback gate (FBG) structure to extend the drain region from the CNT/metal contact to the proximate CNT channels to suppress the tunneling current. Sub-400-nm-channel-length FETs with a FBG structure statistically present a high on/off ratio of up to 104 and a sub-200 mV/dec SS under a high drain bias of up to −2 V while maintaining a high on-state current of 0.2 mA/µm or a peak transconductance of 0.2 mS/µm. By lowering the supply voltage to 1.5 V, FBG CNT-film FETs can meet the requirement of standard-performance ultra large scale integrated circuits (ULSICs). Therefore, the introduction of the drain engineering structure enables applications of CNT-film-based FETs in ULSICs and could also be widely extended to other small-bandgap semiconductor-based FETs for an improvement in their off-state property.

Scalable Perimeter Control Strategy of Road Network Based on the Macroscopic Fundamental Diagram

To alleviate regional traffic congestion in large areas of the urban zonal road network, an extensible perimeter control strategy based on the macroscopic fundamental diagram is proposed to improve the effectiveness of the entire urban network. The proposed strategy considers the fleet storage capacity of the links, avoids over queuing, and establishes a constraint of perimeter control and a regional feedback control model. A new extended boundary is formed by dynamically adjusting the control boundary of the protected area in real time, and a feedback gate is set at the junction of extended boundary to restrict the traffic flow in the road network of the congested area. To verify the effectiveness of the proposed strategy, a Sioux Falls test network is used as the research area, and the effect of the proposed strategy is evaluated in Vissim. Simulation results show that the implementation of the scalable perimeter control strategy improves the operation index of the road network, and a wide range of congestion is obviously alleviated.

Low-phase-noise CMOS VCO with new drain–gate feedback path

In this paper a new LC oscillator without tail current source with an impedance transformation block (ITB) has been presented. Using this ITB, the noise generation from active devices is reduced. The cross-coupled transistors remain mostly in the saturation region and prevent decreasing of LC-tank quality factor. Moreover this structure benefits from more relaxed start-up condition as compared to the conventional LC oscillators and preserves its low phase-noise performance even in low voltage operation. This oscillator is designed and simulated in 0.18 µm CMOS process. The simulation results show that the proposed oscillator achieved a phase noise between ź138.5 and ź141.2 dBc/Hz at 3 MHz frequency offset with 23 % tuning range between 4.61 and 5.79 GHz. The corresponding Figure-of-merit in this tuning range is between ź189.1 and ź192.1 dBc/Hz which is among the best reported performance in comparison to the other state of the arts designs.

An Area-Efficient Clamp Based on Transmission Gate Feedback Technology for Power Rail Electrostatic Discharge Protection

An area-efficient clamp based on transmission gate feedback technology is presented for power rail electrostatic discharge (ESD) protection. With this novel design, only a time constant of 10 ns is required for triggering and keeping the clamp turn-on during an ESD event. Full chip ESD protection with this design can endure a human body model pulse of 4500 V. Compared with the conventional clamp with the same area, the proposed clamp has 28% improvement in ESD protection capability. Simulation results show that there is no mistriggering problem caused by power-on pulse and power noise.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

High-Power Recessed-Gate AlGaN–GaN HFET With a Field-Modulating Plate

Recessed-gate AlGaN-GaN heterojunction field-effect transistors (FETs) with a field-modulating plate (FP) have been successfully fabricated for high-voltage and high-power microwave applications. The developed recessed-gate FP-FET with a gate length of 1 /spl mu/m exhibited an increased transconductance of 200 mS/mm. A series of current collapse measurements revealed that the recessed-gate FP-FET is highly desirable for collapse-free high-voltage power operation. Equivalent circuit analysis demonstrated that the gain loss due to the additional gate feedback capacitance associated with the FP electrode is considerably compensated by increasing the drain bias voltage to more than 30 V. A 48-mm-wide recessed-gate FP-FET biased at a drain voltage of 48 V exhibited a record saturated output power of 197 W with a linear gain of 10.1 dB and a power-added efficiency of 67% at 2 GHz.

Monolithic Distributed Amplifier With Active Control Schemes for Optimum Gain and Group-Delay Flatness, Bandwidth, and Stability

In this paper, active control schemes are presented to optimize the performance of the distributed amplifier (DA) subject to the process variation. A detailed analysis of the DA with mismatched termination loads has been performed, which reveals that pronounced gain and group-delay ripple arises at the low-frequency end from the reflected waves in the artificial transmission line. To solve this problem, an active variable resistor is proposed as the gate-line termination load. The gain and stability of the cascode DA has also been analyzed, which identifies the most critical component determining the tradeoff between the gain-bandwidth product (GBP) and the stability to be the gate feedback resistor of common-gate field-effect transistor. It is also replaced with the active resistor to maximize GBP, while avoiding oscillations. A nine-section cascode DA with active control features is designed and fabricated using commercial GaAs pseudomorphic high electron-mobility transistor foundry. The measurement shows that the gain and group-delay ripple can be minimized, and GBP can be maximized without oscillations by the active bias controls. Active control schemes allow the monolithic DAs to be fine tuned after the fabrication and, thus, can be a robust DA design methodology against process variation and inaccurate device models.