Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

Abstract

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.