Faulty Circuit Research Articles

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection. We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences.

Fault Diagnosis for Analog Circuits by Using EEMD, Relative Entropy, and ELM.

This paper presents a novel fault diagnosis method for analog circuits using ensemble empirical mode decomposition (EEMD), relative entropy, and extreme learning machine (ELM). First, nominal and faulty response waveforms of a circuit are measured, respectively, and then are decomposed into intrinsic mode functions (IMFs) with the EEMD method. Second, through comparing the nominal IMFs with the faulty IMFs, kurtosis and relative entropy are calculated for each IMF. Next, a feature vector is obtained for each faulty circuit. Finally, an ELM classifier is trained with these feature vectors for fault diagnosis. Via validating with two benchmark circuits, results show that the proposed method is applicable for analog fault diagnosis with acceptable levels of accuracy and time cost.

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.

Orthogonal Matching Pursuit on Faulty Circuits

With the wide recognition that modern nanoscale devices will be error-prone, characterization of reliability of information processing systems built out of unreliable components has become an important topic. In this paper, we analyze the performance of orthogonal matching pursuit (OMP), a popular sparse recovery algorithm, running on faulty circuits. We identify sufficient conditions for correct recovery of the signal support and express these conditions in terms of the relationship among signal magnitudes, sparsity, and the mutual incoherence of the measurement matrix. We study both the effects of additive errors in arithmetic computations and logical errors in comparators. We find that the additive errors in the OMP computations have an impact on the overall performance comparable to that of the additive noise in the input measurements. We also show that parallel structures are more robust to logical errors than serial structures in the implementation of a noisy arg max operation, and thus lead to a better OMP performance.

Test Generation Algorithm Based on SVM with compressing Sample Space Methods

Test generation algorithm based on the SVM (support vector machine) generates test signals derived from the sample space of the output responses of the analog DUT. When the responses of the normal circuits are similar to those of the faulty circuits (i.e., the latter have only small parametric faults), the sample space is mixed and traditional algorithms have difficulty distinguishing the two groups. However, the SVM provides an effective result. The sample space contains redundant data, because successive impulse-response samples may get quite close. The redundancy will waste the needless computational load. So we propose three difference methods to compress the sample space. The compressing sample space methods are Equidistant compressional method, k-nearest neighbors method and maximal difference method. Numerical experiments prove that maximal difference method can ensure the precision of the test generation.

Soft‐fault diagnostic method based on locus circle of steady‐state node‐voltage vector

SummaryThis study describes a relationship between an element parameter and a fault feature steady‐state node‐voltage vector (SSNVV). The locus of the SSNVV endpoints is proposed and proven to be an arc of circle under certain conditions, whereas the element parameter varies from small to large within a certain range. The arc of circle is called locus circle of SSNVV (LCoSSNVV). An LCoSSNVV‐based soft‐fault diagnostic method is also proposed. The method utilizes three discrete SSNVV endpoints to draw an LCoSSNVV for each element and collects all LCoSSNVVs to produce an LCoSSNVV set for fault diagnosis. In the following diagnostic process, the method measures a fault feature SSNVV of actual faulty circuit and judges which element is faulty on the basis of the relationship between the measured fault feature SSNVV and the LCoSSNVVs in an LCoSSNVV set. Subsequently, the fault can be further subdivided into different types of soft faults on the basis of the relative position of the SSNVV on the LCoSSNVV. A range of the faulty element parameter value can be estimated. Several examples illustrate the method. A measurement solution of SSNVV and a solution of a programming strategy are described. The new LCoSSNVV‐based method would effectively improve the soft‐fault diagnosis process of a linear time‐invariant circuit network. Copyright © 2015 John Wiley & Sons, Ltd.

The On-line Evolutionary Method for Soft Fault Diagnosis in Diode-transistor Circuits

Abstract The paper is devoted to diagnostic method enabling us to perform all the three levels of fault investigations - detection, localization and identification. It is designed for analog diodetransistor circuits, in which the circuit’s state is defined by the DC sources’ values causing elements operating points and the harmonic components with small amplitudes being calculated in accordance with small-signal circuit analysis rules. Gene expression programming (GEP), differential evolution (DE) and genetic algorithms (GA) are a mathematical background of the proposed algorithms. Time consumed by diagnostic process rises rapidly with the increasing number of possible faulty circuit elements in case of using any of mentioned algorithms. The conncept of using two different circuit models with partly different elements allows us to decrease a number of possibly faulty elements in each circuit because some of possibly faulty elements are absent in one of two investigated circuits

Aircraft electric system intermittent arc fault detection and location

Intermittent arc faults appear in aircraft power systems in unpredictable ways when the degraded wires are wet, vibrating against metal structures, or under mechanical stresses. They could evolve into serious faults that may cause onboard fires, power interruptions, system damage and catastrophic incidents, and thus have raised concern. Recent trends in solid state power controllers (SSPCs) motivated the development of nondestructive diagnostic methods for health monitoring of aircraft wiring. In this paper, the ABCD matrix (or transmission matrix) modeling method is introduced to derive normal and faulty load circuit models with better accuracy and reduced complexity compared to the differential equation approach, and an intermittent arc fault detection method is proposed based on temporary deviations of load circuit model coefficients and wiring parameters. Furthermore, based on the faulty wiring model, a genetic algorithm is proposed to estimate the fault-related wiring parameters such as intermittent arc location and average intermittent arc resistance. The proposed method can be applied to both the alternating current power distribution system (PDS) and the direct current (DC) PDS. Experiments using a DC power source have been conducted, and the experimental results have demonstrated effectiveness of the proposed method.

PSO Based Feature Extraction Method for Analog Circuits Fault Information

In order to improve the diagnosis efficiency of faulty circuits with tolerance and to ameliorate characteristic description of faulty symptom, the faulty features of the circuit with tolerance are created by information entropy method at first, and then feature extraction method based on discrete Particle Swarm Optimization algorithm (PSO) is proposed to obtain the optimal feature subset of faulty feature. At last, the optimal feature subset is used to train the classifier to diagnosis the faults of the circuit with tolerance. Experiments results show the validity of this proposed method.

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs

In this paper a simulator of soft errors (SEUs) in the configuration memory of SRAM-based FPGAs is presented. The simulator, named ASSESS, adopts fault models for SEUs affecting the configuration bits controlling both logic and routing resources that have been demonstrated to be much more accurate than classical fault models adopted by academic and industrial fault simulators currently available. The simulator permits the propagation of faulty values to be traced in the circuit, thus allowing the analysis of the faulty circuit not only by observing its output, but also by studying fault activation and error propagation. ASSESS has been applied to several designs, including the miniMIPS microprocessor, chosen as a realistic test case to evaluate the capabilities of the simulator. The ASSESS simulations have been validated comparing their results with a fault injection campaign on circuits from the ITC'99 benchmark, resulting in an average error of only 0.1%.

Comparative Power Analysis of LFSR Test Pattern Generators

Automatic Test Pattern Generation Automatic Test Pattern Generator is an electronic de-sign automation method used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The designs selected for comparison use LFSR as its core central component around which the entire algorithms are based which contribute in construction of Automatic test pattern generator. The LFSR is considered as it gives excellent random characteristics and has a low area overhead which allows it to be placed in the integrated circuit

Android platform based smartphones for a logistical remote association repair framework.

The maintenance of large-scale systems is an important issue for logistics support planning. In this paper, we developed a Logistical Remote Association Repair Framework (LRARF) to aid repairmen in keeping the system available. LRARF includes four subsystems: smart mobile phones, a Database Management System (DBMS), a Maintenance Support Center (MSC) and wireless networks. The repairman uses smart mobile phones to capture QR-codes and the images of faulty circuit boards. The captured QR-codes and images are transmitted to the DBMS so the invalid modules can be recognized via the proposed algorithm. In this paper, the Linear Projective Transform (LPT) is employed for fast QR-code calibration. Moreover, the ANFIS-based data mining system is used for module identification and searching automatically for the maintenance manual corresponding to the invalid modules. The inputs of the ANFIS-based data mining system are the QR-codes and image features; the output is the module ID. DBMS also transmits the maintenance manual back to the maintenance staff. If modules are not recognizable, the repairmen and center engineers can obtain the relevant information about the invalid modules through live video. The experimental results validate the applicability of the Android-based platform in the recognition of invalid modules. In addition, the live video can also be recorded synchronously on the MSC for later use.

Failure modes of synthetic test circuits used to evaluate the current interruption capability of high-voltage circuit breakers

Summary This paper deals with different failure mechanisms in a synthetic test circuit, which may lead to faulty interpretation of the results achieved using such a synthetic test circuit to evaluate the current interruption capability of high-voltage circuit breakers. These include transient insulation failure in different components of synthetic test circuits supposed to high voltage as well as imperfect operation of various switches. Different failure modes are simulated and it has been shown that the simulation results match the waveforms measured in faulty operational circuits. The results of this paper make it possible to distinguish different failure modes of such circuits based on the measured current and voltage waveforms. Copyright © 2014 John Wiley & Sons, Ltd.

Unknown Output Values of Faulty Circuits and Output Response Compaction

When using output response compaction it is necessary to address the fact that circuits may produce unknown output values. Methods to address this issue ensure that the output response compactor would produce a unique fault-free signature that can be used for fault detection. This paper considers the unknown output values that are produced by faulty circuits. If a faulty circuit produces an unknown value when the output value of the fault-free circuit is known, the unknown faulty output value may affect the computation of a signature. The faulty signature may not be unique, and it may not always be different from a fault-free signature. The ability to verify that the fault will be detected based on its signature is thus lost. Without limiting the discussion to a particular output response compactor, the paper studies the prevalence of such faults in benchmark circuits, the prevalence of unknown faulty output values for which the corresponding fault-free values are known, and the effects of addressing this issue.

Symbolic analysis of faulty logic circuits under correlated data-dependent gate failures

In this paper we present a method for symbolic analysis of unreliable logic circuits in the presence of correlated and data-dependent gate failures, described by Markov chains. Furthermore, using this method we investigate the influence of data-dependent failures on the performance of majority logic and multiple input XOR gates.

Diagnostics and Prognostics Method for Analog Electronic Circuits

Analog circuits play a vital role in ensuring the availability of industrial systems. Unexpected circuit failures in such systems during field operation can have severe implications. To address this concern, we developed a method for detecting faulty circuit condition, isolating fault locations, and predicting the remaining useful performance of analog circuits. Through the successive refinement of the circuit's response to a sweep signal, features are extracted for fault diagnosis. The fault diagnostics problem is posed and solved as a pattern recognition problem using kernel methods. From the extracted features, a fault indicator (FI) is developed for failure prognosis. Furthermore, an empirical model is developed based on the degradation trend exhibited by the FI. A particle filtering approach is used for model adaptation and RUP estimation. This method is completely automated and has the merit of implementation simplicity. Case studies on two analog filter circuits demonstrating this method are presented.

Kalman Filter Based Method for Fault Diagnosis of Analog Circuits

Abstract This paper presents a Kalman filter based method for diagnosing both parametric and catastrophic faults in analog circuits. Two major innovations are presented, i.e., the Kalman filter based technique, which can significantly improve the efficiency of diagnosing a fault through an iterative structure, and the Shannon entropy to mitigate the influence of component tolerance. Both these concepts help to achieve higher performance and lower testing cost while maintaining the circuit.s functionality. Our simulations demonstrate that using the Kalman filter based technique leads to good results of fault detection and fault location of analog circuits. Meanwhile, the parasitics, as a result of enhancing accessibility by adding test points, are reduced to minimum, that is, the data used for diagnosis is directly obtained from the system primary output pins in our method. The simulations also show that decision boundaries among faulty circuits have small variations over a wide range of noise-immunity requirements. In addition, experimental results show that the proposed method is superior to the test method based on the subband decomposition combined with coherence function, arisen recently.

Homeostatic Responses Fail to Correct Defective Amygdala Inhibitory Circuit Maturation in Fragile X Syndrome

Fragile X syndrome (FXS) is a debilitating neurodevelopmental disorder thought to arise from disrupted synaptic communication in several key brain regions, including the amygdala, a central processing center for information with emotional and social relevance. Recent studies reveal defects in both excitatory and inhibitory neurotransmission in mature amygdala circuits in Fmr1(-/y) mutants, the animal model of FXS. However, whether these defects are the result of altered synaptic development or simply faulty mature circuits remains unknown. Using a combination of electrophysiological and genetic approaches, we show the development of both presynaptic and postsynaptic components of inhibitory neurotransmission in the FXS amygdala is dynamically altered during critical stages of neural circuit formation. Surprisingly, we observe that there is a homeostatic correction of defective inhibition, which, despite transiently restoring inhibitory synaptic efficacy to levels at or beyond those of control, ultimately fails to be maintained. Using inhibitory interneuron-specific conditional knock-out and rescue mice, we further reveal that fragile X mental retardation protein function in amygdala inhibitory microcircuits can be segregated into distinct presynaptic and postsynaptic components. Collectively, these studies reveal a previously unrecognized complexity of disrupted neuronal development in FXS and therefore have direct implications for establishing novel temporal and region-specific targeted therapies to ameliorate core amygdala-based behavioral symptoms.

Impaired recruitment of seizure-generated neurons into functional memory networks of the adult dentate gyrus following long-term amygdala kindling

Epileptic seizures increase the birth of new neurons in the adult hippocampus. Although the consequences of aberrant neurogenesis on behavior are not fully understood, one hypothesis is that seizure-generated neurons might form faulty circuits that disrupt hippocampal functions, such as learning and memory. In the present study, we employed long-term amygdala kindling (i.e., rats receive 99-electrical stimulations) to examine the effect of repeated seizures on hippocampal neurogenesis and behavior. We labeled seizure-generated cells with the proliferation marker BrdU after 30-stimulations and continued kindling for an additional 4weeks to allow newborn neurons to mature under conditions of repeated seizures. After kindling was complete, rats were tested in a trace fear conditioning task and sacrificed 2h later to examine if 4-week old newborn cells were recruited into circuits involved in the retrieval of emotional memory. Compared to non-kindled controls, long-term kindled rats showed significant impairments in fear memory reflected in a decrease in conditioned freezing to both tone and contextual cues during testing. Moreover, long-term kindling also prevented the activation of 4-week old newborn cells in response to fear memory retrieval. These results indicate that the presence of seizure activity during cell maturation impedes the ability of new neurons to integrate properly into circuits important in memory formation. Together, our findings suggest that aberrant seizure-induced neurogenesis might contribute to the development of learning impairments in chronic epilepsy and raise the possibility that targeting the reduced activation of adult born neurons could represent a beneficial strategy to reverse cognitive deficits in some epileptic patients.

Fault Diagnosis of Analog Circuits Using Systematic Tests Based on Data Fusion

An analog fault diagnosis approach using a systematic step-by-step test is proposed for fault detection and location in analog circuits with component tolerance and limited accessible nodes. First, by considering soft faults and component tolerance, statistics-based fault detection criteria are established to determine whether a circuit is faulty by measuring accessible node voltages. For a faulty circuit, fuzzy fault verification is performed using the accessible node voltages. Furthermore, using an approximation technique, the most likely faulty elements are identified with a limited number of circuit gain measurements at selected frequencies. Finally, employing the D-S evidence theory, synthetic decision is made to locate faults according to the results of fault verification and estimation. Unlike other methods which use a single diagnosis method or a particular type of measurement information, the proposed approach makes use of the redundancy of different types of measurement information and the combined use of different diagnosis methods so as to improve diagnosis accuracy.