Faults In Random Access Memories Research Articles

March test algorithm for unlinked static reduced three-cell coupling faults in random-access memories

A memory fault model regarding the unlinked static three-cell coupling faults in n × 1 random-access memories is discussed. This model is an extension of the well-known model of unlinked static two-cell coupling faults. Because this model of three-cell coupling is limited to the physically neighbouring memory cells, it can also be considered a neighbourhood pattern-sensitive model. An efficient march test algorithm able to cover this reduced model of three-cell coupling is presented in this letter.

Window Based Input Vector Monitoring Concurrent BIST Using SRAM Cells with Diagnostic Data Compression

Window based Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without the requirement to set the circuit offline to perform the test. It is evaluated based on the hardware overhead and the concurrent test latency (CTL). This thesis makes an attempt using novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set of vectors called windows, and the use of a static-RAM like structure. To detect Static Faults in Random Access Memories, proposed a BIST architecture with the capability of hamming syndrome compression. To reduce the diagnostic data volume, a new idea of March element based (MEB)compression is proposed in this BIST Architecture. The data to be diagnosed in a RAM tested with a March test can be efficiently compressed by the MEB compression scheme. The scheme with SRAM cells is shown to perform the detection of error, error location and the error bit position in that location successfully. The software simulation is carried out in ModelSim SE PLUS 6.2b and Xilinx 14.2i design suite. FPGA implementation is done in Xilinx Spartan 3E kit and the output is verified.

March Test for Static Neighborhood Pattern-Sensitive Faults in Random-Access Memories

A multibackground March test (March-76N) for a model of static neighborhood pattern sensitive faults (NPSFs) in N ´ 1 random-access memories is presented. March-76N is able to cover both simple and linked NPSFs. As any other test dedicated to the NPSFs, March-76N assumes that the storage cells are arranged in a rectangular grid and the mapping from logical addresses to physical cell locations is known completely. With a length of 76N, this March test is more efficient than other published tests dedicated to this model. Ill. 4, bibl. 16, tabl. 4 (in English; abstracts in English and Lithuanian).DOI: http://dx.doi.org/10.5755/j01.eee.119.3.1369

March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories

A fault primitive-based analysis of all static simple (i.e., not linked) three-cell coupling faults in n×1 random-access memories (RAMs) is discussed. All realistic static coupling faults that have been shown to exist in real designs are considered: state coupling faults, transition coupling faults, write disturb coupling faults, read destructive coupling faults, deceptive read destructive coupling faults, and incorrect read coupling faults. A new March test with 66 n operations able to detect all static simple three-cell coupling faults is proposed. To compare this test with other industrial March tests, simulation results are also presented in this paper.

Injection of functional faults into VHDL descriptions of random-access memory devices

The present article considers the problem of describing models of functional faults of random-access memory devices by means of the VHDL language. A technique of injecting models of faults in random-access memory in the design descriptions of digital devices in the VHDL language is proposed. It is shown that the proposed technique may be applied for evaluating the behavior of a digital device when there are defects present, as well as for verification of testing algorithms for random-access memory devices.

Generation of address sequences for effective random access memory testing

In the present article the problem of efficient application of multiple march tests for the purpose of detecting faults in random access memory, realized through the generation of different address sequences, is considered. For these purposes, a new algorithm for generating address sequences is proposed and the efficiency gained from its application evaluated. In the conclusion experimental results on the use of the proposed method for generating address sequences are presented and the efficiency of the method in multiple run random access memory tests is demonstrated.

Minimal March Tests for Detection of Dynamic Faults in Random Access Memories

The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of Random Access Memories (RAM) with significant impact on defect-per-million (DPM) levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operation single-cell and two-cell dynamic faults, respectively, were proposed recently [Benso et al., Proc., ITC 2005] improving the length of the corresponding tests proposed earlier [Hamdioui et al., Proc. of IEEE VLSI Test Symposium, pp. 395---400, 2002]. Also, a March test of length 100N was proposed [Benso et al., Proc. ETS 2005, Tallinn, pp. 122---127, 2005] for detection of two-cell dynamic faults with two fault-sensitizing operations both applied on the victim or aggressor cells. In this paper, for the first time, March test algorithms of minimum length are proposed for two-operation single-cell and two-cell dynamic faults. In particular, the previously known March test algorithm of length 100N for detection of two-operation two-cell dynamic faults is improved by 30N.

Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories

This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the coupling faults between physically adjacent memory cells have been considered. The tests assume that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known completely. The march tests need 30n and 41n operations, respectively. In this paper any memory fault is modelled by a set of primitive memory faults called simple faults. We prove, using an Eulerian graph model, the ability of the test algorithms to detect all simple coupling faults. This paper also includes a study regarding the ability of the test MT-R3CF to detect interacting linked 3-coupling faults. This work improves the results presented in [1] where a similar model of reduced 3-coupling faults has been considered and a march test with 38n operations has been proposed. To compare these new march tests with other published tests, simulation results are presented in this paper.

Linked Faults in Random Access Memories: Concept, Fault Models, Test Algorithms, and Industrial Results

The analysis of linked faults (LFs), which are faults that influence the behavior of each other, such that masking can occur, has proven to be a source for new memory tests, characterized by an increased fault coverage. However, many newly reported fault models have not been investigated from the point-of-view of LFs. This paper presents a complete analysis of LFs, based on the concept of fault primitives, such that the whole space of LFs is investigated and accounted for and validated. Some simulated defective circuits, showing linked-fault behavior, will be also presented. The paper establishes detection conditions along with new tests to detect each fault class. The tests are merged into a single test March SL detecting all considered LFs. Preliminary test results, based on Intel advanced caches, show that its fault coverage is high as compared with all other traditional tests and that it detects some unique faults; this makes March SL very attractive industrially.

Efficient march test for 3-coupling faults in random access memories

A new efficient march test algorithm for detecting the 3-coupling faults in Random Access Memories (RAM) is given in this paper. To reduce the length of the test algorithm only the 3-coupling faults between physically adjacent memory cells have been considered. The proposed test algorithm needs 38N operations. We have proved, using an Eulerian graph model, that the algorithm detects all non-interacting coupling faults. This paper also comprises a study about the ability of the algorithm to cover the interacting coupling faults. Simulation results with regard to the coupling fault coverage of the march tests, obtained based on a fault injection mechanism, are also presented in this paper.

An algebra of multiple faults in RAMs

Cell array faults in random-access memories (RAMs) are usually represented by Mealy automata. In such a model, multiple faults should also be representable by automata; in fact, it should be possible to compute the automaton representing a multiple fault from the automata representing the single faults that make up the multiple fault. In this paper we study properties of binary composition operations on automata that are appropriate for the representation of multiple faults in RAMs. First, we derive a set of generic conditions that every composition operation must satisfy. Second, we develop a set of physical conditions that the composition must satisfy in order to apply to stuck-at, transition and coupling faults in RAMs. Third, we represent the transition table rules used by van de Goor and Smit by a composition operation and prove that this operation satisfies both the generic and physical conditions. Fourth, we point out that in some circumstances, it is appropriate to use a different composition operation (defined by us in a previous paper) to permit a different handling of coupling faults in the presence of stuck-at or transition faults. We compare and relate the properties of the two algebras.

Deterministic tests for detecting singleV-coupling faults in RAMs

We consider the problem of detecting singleV-coupling faults (as defined by Nair, Thatte, and Abraham) inn×1 random-access memories (RAMs). First we derive a lower bound of 2 V−2 nlog2 n+(2 V +3)n on the length of any test that detects all singleV-coupling faults, for 2≤V≤47 andn=2 e whereeɛ{8,...,34}. In the derivation we make use of a family of binary codes which we call (n, θ)-exhaustive codes. We then describe a procedure which, given any (n, V−1)-exhaustive code, constructs a test that detects all singleV-coupling faults, forn≥V>2. Following this approach, optimal (n,1)- and (n, 2)-exhaustive codes are used to construct S2CTEST and S3CTEST, which are efficient tests of length 10n and 4nlog2 n+18n that detect all single 2- and 3-coupling faults, respectively. S3CTEST is roughly five times shorter, for current RAM capacities, than Papachristou and Sahgal's test of length 24n[log2 n]+n. Codes generated according to Tang and Chen are used similarly to construct S4CTEST and S5CTEST, which are tests of approximate length 8.6n(log2 n)1.585 and 9.6n(log2 n)2.322 that detect all single 4- and 5-coupling faults, respectively. S5CTEST has the interesting property of being able to detect all single physical neighborhood pattern-sensitive faults without requiring the mapping from logical cell addresses to physical cell locations. S5CTEST also detects the scrambled pattern-sensitive fault recently proposed by Franklin and Saluja; moreover, the new test is approximately fourteen times shorter (for 1 and 4 Mbit RAMs) than the test they describe.

Near-optimal tests for classes of write-triggered coupling faults in RAMs

This article is concerned with the detection of write-triggered coupling faults and toggling faults (certain double coupling faults) in n × 1 random-access memories (RAMs), where n is the number of one-bit words in the memory. In an earlier article we showed that any functional test that detects all multiple coupling faults must have a length of at least 2n 2 + 3n. Since such a test is prohibitively long, given modern RAM capacities, we study more manageable subclasses of the class of all coupling faults. We show that there exist two hierarchies of fault models corresponding to nested subclasses of toggling faults and coupling faults, respectively, of increasing maximum multiplicities. We then identify optimal or near-optimal tests for two classes of toggling faults and five classes of coupling faults; these tests are of order n or nlog2 n.

Detection of coupling faults in RAMs

This article presents results fundamental to the problem of detecting coupling faults in random access memories (RAMs). Good and faulty memories are represented as Mealy automata using the formal framework for sequential machine testing developed by Brzozowski and Jurgensen. A precise description of the coupling fault is used to define two fault models: “general coupling,” which is the set of all possible multiple coupling faults, and “general toggling,” which is a subset of general coupling. A lower bound of 2n2 + n is derived on the length of any test that detects general toggling in an n cell memory; a test by Marinescu is thereby shown to be optimal for this fault model. A lower bound of 2n2 + 3n is derived on the length of any test that detects general coupling, and a corresponding test of length 2n2 + 4n is described. Abadir and Reghbati's improved version of the traditional test GALPAT, of length 4n2 + 4n, is shown to detect general toggling but not general coupling.

Diagnosis and repair of memory with coupling faults

The problem of diagnosis and spare allocation for random-access memory (RAM) with coupling faults is addressed. A number of spare allocation algorithms for RAM with row and column redundancy have recently been proposed. These procedures, however, have been restricted to repair stuck-at faults. The authors examine both diagnosis and repair of coupling faults in RAMs utilizing spare rows and columns. It is shown that a coupling fault is repaired if its coupling cell is replaced by utilizing a spare row or its coupled cell is replaced by utilizing a spare row or column. By specifying both the coupled cell and coupling cell, the amount of redundancy required to repair a given set of faults may be reduced. A diagnosis procedure for RAM is provided to locate stuck-at faults as well as coupling faults. A graph model is used to describe the repair of coupling faults. A repair procedure has been implemented to allocate rows and columns for repair. >

A Graph Model for Pattern-Sensitive Faults in Random Access Memories

This correspondence generalizes Hayes' recent ideas for generating an optimal transition write sequence which forms the backbone of his algorithm for testing semiconductor RAM's for pattern-sensitive faults. The generalization, presented in graph theoretic terms, involves two sequential steps. The frmst step results in assigning of a to each memory cell. In the second step, each color is defined as a distinct sequence of bits representing the sequence of states assumed by the correspondingly colored cell. The constraints imposed at each step lead to interesting and general problems in graph theory: the standard graph coloring problem in the first step, and a path projection problem from a binary m-cube to a subcube in the second step. Applications to arbitrary k-cell neighborhoods, and particularly to three-cell neighborhoods are shown.

Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"

An efficient, optimal test sequence for detecting multiple stuck-at faults in random access memories (RAM's) for any decoder implementation is presented. Another algorithm which does not assume any particular wired logic behavior of simultaneously accessed storage locations, is also presented.

An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories

This correspondence presents an optimal algorithm to detect any single "stuck-at-i," "stuck-at-O" fault and any combination of "stuck-at-I," "stuck-at-O" multiple faults in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2n memory accesses.