Injection of functional faults into VHDL descriptions of random-access memory devices

Abstract

The present article considers the problem of describing models of functional faults of random-access memory devices by means of the VHDL language. A technique of injecting models of faults in random-access memory in the design descriptions of digital devices in the VHDL language is proposed. It is shown that the proposed technique may be applied for evaluating the behavior of a digital device when there are defects present, as well as for verification of testing algorithms for random-access memory devices.