Window Based Input Vector Monitoring Concurrent BIST Using SRAM Cells with Diagnostic Data Compression

Abstract

Window based Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without the requirement to set the circuit offline to perform the test. It is evaluated based on the hardware overhead and the concurrent test latency (CTL). This thesis makes an attempt using novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set of vectors called windows, and the use of a static-RAM like structure. To detect Static Faults in Random Access Memories, proposed a BIST architecture with the capability of hamming syndrome compression. To reduce the diagnostic data volume, a new idea of March element based (MEB)compression is proposed in this BIST Architecture. The data to be diagnosed in a RAM tested with a March test can be efficiently compressed by the MEB compression scheme. The scheme with SRAM cells is shown to perform the detection of error, error location and the error bit position in that location successfully. The software simulation is carried out in ModelSim SE PLUS 6.2b and Xilinx 14.2i design suite. FPGA implementation is done in Xilinx Spartan 3E kit and the output is verified.