Interconnect Faults Research Articles

Lifetime Estimation of Moems Devices

Generally, microelectro mechanical systems (MOEMS) devices require encapsulation for protecting their fragile and tiny inner components in a hermetically sealed cavity. Cavity hermeticity can be critical to the device performance and plays a vital role with respect to reliability and long-term drift characteristics of the MOEMS products. The paper presents a theoretical approach for estimation of lifetime of MOEMS devices in terms of cavity’s hermeticity to gases and water. The results are summarized as working maps for MOEMS packaging engineers, in terms of device cavity (internal package volume), equivalent leak rates, and equivalent size of interconnected defects in the bonding zone.

An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults

We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIST structure contains self-enabling test pattern generators, self-configurable switch matrices, and response analyzers that all work together and reprogram themselves without any external intervention. This eliminates downloading configuration bitstreams into the FPGA after the start of testing and, hence, reduces test time. Our technique requires only six different switch matrix configurations to test the interconnect, which is fewer than prior methods, while retaining good diagnostic resolution. The area overhead to add self-configurable test structures to Xilinx FPGAs is as low as 0.5%.

A Test Structure for Contact and Via Failure Analysis in Deep-Submicrometer CMOS Technologies

Reliability and yield of CMOS integrated circuits are becoming more and more dependent on interconnect elements (contacts, vias, and metal lines). These are therefore considered to represent one of the main limits to the future scaling down of integration processes. Indeed, the continuous growth of semiconductor technology integration density has led to billions of transistorson a single chip and, hence, the evaluation of process yield asks for failure rate sensitivity in the order of 1 fault per billion. This paper presents a test structure which allows evaluating the contribution of interconnects to reliability and manufacturing yield degradation in high-density CMOS technologies. The test structure is based on a suitable array of contacts and vias, and has been conceived to measure the statistical distribution of interconnect failures. The main advantages of the proposed test structure are: the reduced number of test pads required measuring an extremely high amount of contacts and vias; the high sensitivity, which allows also resistive contacts or vias to be identified; and the possibility to determine the physical location of interconnect faults, thus simplifying the subsequent physical failure analysis. The test structure was integrated in 130 nm CMOS technology. Experimental results demonstrate the effectiveness of the proposed solution.

A method for detecting interconnect DSM defects in systems on chip

This paper presents a built-in test method targeting interconnect defects using I/sub DDT/ testing, delay testing, and boundary scan. It was learned that I/sub DDT/ testing is an effective way to detect open and short defects. Boundary scan can provide accessibility to internal buses inside a chip. A statistical analysis method eases the uncertain factors due to process variations and power fluctuation. This paper also includes the experimental data using the proposed techniques to detect shorts, opens, or the other non-stuck-at fault type defects.

Correlation of electromigration defects in small damascene Cu interconnects with their microstructure

Limited reliability of interconnect material mainly due to current induced electromigration defects is one of the serious issues of actual and future microelectronic devices. The influence of interfaces and microstructure on electromigration damage in Cu interconnects became an open question again and needs further studies. In order to find correlations between microstructural details and localization of electromigration defects generated in narrow electroplated Cu lines, microstructure of entire line was recorded by electron back scatter diffraction measurements with high lateral resolution, and then electromigration test was performed in high vacuum under direct SEM observation. In the result, a number of hillocks were found to have grown in the vicinity of (1 0 0) grains having at least one high angle grain boundary around it. Fatal voids often formed at the cathode end and produced dielectric cracking in some cases. Furthermore, voiding started from the sidewall of interconnect trenches mostly at such places where (1 1 1) grains with high angle grain boundaries were located.

Built-in self-test of global interconnects of field programmable analog arrays

Strategies for the test of Field Programmable Analog Arrays (FPAAs) have been devised based on testing separately their main three components: configurable analog blocks, I/O pads and interconnection network. In this work, a scheme for testing the interconnection network, in particular the global wiring, is presented. As long as analog wiring is considered, catastrophic faults at the switches and wires are considered, as well as parametric capacitive or resistive defects in interconnects. Similarly to FPGAs, critical path search is based on a graph model, so that known algorithms are reused, yielding a minimum number of Test Configurations. Then, a near-zero area overhead BIST procedure is proposed, in which Analog Built-in Block Observers are implemented as oscillators and integrators, respectively, generating test stimuli and analyzing output responses, using internal configurable resources of the FPAA.

Fault tolerance of switch blocks and switch block arrays in FPGA

A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications. Two criteria are proposed and used as figure-of-merit for evaluating different FPGA interconnect architectures. The proposed approach is based on the number of available paths between pairs of end points and the probability to establish a one-to-one mapping between all input and output end points. A probabilistic approach is also presented to evaluate the fault-tolerant routing of the entire FPGA by connecting switch blocks in chains, as required for testing and to account for the input-output (I/O) pin restrictions of an FPGA chip. All possible interconnect faults for programmable switches and wiring channels are considered in the fault model. The proposed method is applicable to arbitrary switch block structures. Experimental results on commercial as well as academic designed FPGAs are presented and analyzed.

Design of a Low Cost IC Tester

Low cost Integrated Circuit (IC) testing is now a burning issue in semiconductor technology. Conventional IC tester, Automatic Test Equipment (ATE), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo-random testing approach of IC testing has been emerged as an economically viable alternative to the expensive deterministic testing approach. This study introduces the design of a System-on-a-chip (Soc) implementing pseudo-random test technique for low cost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-port facilities efficiently. It can also be used for testing Printed Circuit Board (PCB) interconnection faults.

An Overview of Molecular Computing Approaches (Part II)

Abstract This is the second part of an article on molecular electronics. The first part, published in the August 2004 issue of EDFA, discussed the development of molecular devices including nanowires, rectifiers, switches, and transistors. Here, the author describes nontraditional molecular computing architectures based on crosspoint arrays, randomized nanocells, and cellular automata. Challenges associated with interconnect demand, lithography alternatives, and defect tolerance are also discussed.

Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

The dielectric constant dependence of the mechanical strength and the adhesion strength is investigated using porosity-controlled low-k films, and a material parameter is clarified to suppress the chemical mechanical polishing (CMP)-related defects in Cu damascene interconnects. Mechanical strengths such as the modulus and hardness of low-k films decreased as the dielectric constant decreased. Adhesion energy between the low-k films and an upper hard-mask layer (HM) of PECVD-SiO2 strongly depends on the dielectric constant of low-k films, while adhesion energy between the low-k films and a lower etch stop layer (ES) of SiCN shows weak dependence. It was found that the adhesion energy between the upper SiO2 and the low-k film is a critical mechanical parameter for diminishing the CMP-related defects. Introducing a porous low-k film, methylsilsesquiazane (k=2.64), with high adhesion to the HM-SiO2, we successfully fabricated single damascene copper interconnects within an acceptable limit of CMP-related defects.

Fault-coverage analysis techniques of crosstalk in chip interconnects

This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in system-level interconnects and buses of deep submicron (DSM) chips. The fast and accurate estimation technique will enable: 1) evaluation of different existing tests, like functional, scan, logic built-in self-test (BIST), and delay tests, for effective testing of crosstalk defects in core-to-core interconnects and 2) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing. Based on a covering relationship we distinguish between transition tests in detecting crosstalk defects and develop an abstract crosstalk fault model for chip interconnects. With this fault model and the covering relationship, we develop a fast and efficient method to estimate the fault coverage of any general test set. We also develop a simulation-based technique to calculate the probability of occurrence of the defects corresponding to each fault, which enables the fault-coverage analysis technique to produce accurate estimates of the actual crosstalk defect coverage of a given test set. The crosstalk test and fault properties, as well as the accuracy of the proposed crosstalk coverage analysis techniques, have been validated through extensive simulation experiments. The experiments also demonstrate that the proposed crosstalk techniques are orders of magnitude faster than the alternative method of SPICE-level simulation. Finally, we demonstrate the practical applicability of the proposed fault-coverage analysis technique by using it to evaluate the crosstalk fault coverage of logic BIST tests for the system-level interconnects and buses in a digital signal processor core.

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern. In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

As IC densities are increasing, cluster-based field programmable gate arrays (FPGA) architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-base architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high-density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect fault detection and diagnosis. This technique enables the detection of bridging faults involving intracluster interconnect and extracluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intracluster configurations separately from extracluster configurations, thereby improving the efficiency of the configuration definition process. The cornerstone of this work is the concise expression of the detectability conditions of each fault and the distinguishability conditions of each fault pair. By guaranteeing that both intracluster and extracluster configurations have several test transparency properties, hierarchical fault detectability is ensured.

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.

Techniques for Localization of IC Interconnection Defects

AbstractThe advances in integrated circuit technology has made failure site localization extremely challenging. Charge-Induced Voltage Alteration (CIVA), Low Energy CIVA (LECIVA), Light-Induced Voltage Alteration (LIVA), Seebeck Effect Imaging (SEI) and Thermally-Induced Voltage Alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy (SEM) techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects. In addition to the techniques listed above, the Resistive Contrast Imaging (RCI) for localizing opens on metal test patterns will be described as a starting point for the “IVA” technologies.

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

In deep-submicron technologies, long interconnects play an ever-important role in determining the performance and reliability of core-based system-on-chips (SoCs). Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC, thereby allowing at-speed testing of interconnect crosstalk defects, while eliminating the need for test overhead and the possibility of over-testing. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.

Analyzing and diagnosing interconnect faults in bus-structured systems

Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models. We propose several methods and strategies for a diagnosis using different fault models, including those applicable to submicron technology. Besides defining new features, such as the logical extent of faults, we also propose a reduction strategy that permits 100% fault detection and identification (including fault location).

Global fault localization using induced voltage alteration

Advances in integrated circuit technology have made failure site localization extremely challenging. Charge-induced voltage alteration (CIVA), low energy CIVA (LECIVA), light-induced voltage alteration (LIVA), Seebeck effect imaging (SEI) and thermally-induced voltage alteration (TIVA) are five recently developed failure analysis techniques which meet the challenge by rapidly and non-destructively localizing interconnection defects on ICs. The techniques take advantage of voltage fluctuations in a constant current power supply as an electron or photon beam is scanned across an IC. CIVA and LECIVA are scanning electron microscopy techniques that yield rapid localization of open interconnections. LIVA is a scanning optical microscopy (SOM) method that yields quick identification of damaged semiconductor junctions and determines transistor logic states. SEI and TIVA are SOM techniques that rapidly localize open interconnections and shorts respectively. LIVA, SEI, and TIVA can be performed from the backside of ICs by using the proper photon wavelength. This paper describes the CIVA, LECIVA, LIVA, TIVA, and SEI techniques in terms of the physics of signal generation, general data acquisition system required, and imaging results displaying the utility of each technique for localizing interconnection defects.

An efficient structural approach to board interconnect diagnosis

In this paper we present an efficient structural approach for diagnosing board interconnects using boundary-scan. Whereas existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in a CMOS circuit environment. The diagnostic test set is generated on the basis of graph theoretic technique and the adjacency fault model is adopted. By using the structural information of the wiring layout, the test length can be reduced. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing or confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan testing.

A Fault Tolerant Technique for FPGAs

In this paper we present a fault tolerant (FT) technique for field programmable gate arrays (FPGAs) that is based on incrementally reconfiguring circuits and applications that have been previously placed and routed. Our technique targets both logic faults and interconnect faults, and our algorithms can be applied to either static or run-time reconfigurable FPGAs. The algorithm for reconfiguring designs in the presence of logic faults uses a matching technique. The matching technique requires no preplaced, spare logic resources and is capable of handling groups of faults. Experimental results indicate there is little or no impact on circuit performance for low numbers of reconfigured logic blocks. For interconnect faults, we present a rip-up and reroute strategy. Our strategy is based on reading back the FPGA configuration memory, so no netlist is required for rerouting around faulty resources. Experimental results indicate high incremental routability for low numbers of interconnect faults. We also lay the foundation for applying our approach to yield enhancement.