Abstract
Low cost Integrated Circuit (IC) testing is now a burning issue in semiconductor technology. Conventional IC tester, Automatic Test Equipment (ATE), cannot cope with the today’s continuously increasing complexities in IC technology. Deterministic algorithm, which is an idea of 1960’s, is adopted in the ATE. Recently pseudo-random testing approach of IC testing has been emerged as an economically viable alternative to the expensive deterministic testing approach. This study introduces the design of a System-on-a-chip (Soc) implementing pseudo-random test technique for low cost IC testing with reliable performance. It is capable of testing combinational circuits as well as sequential circuits with scan-port facilities efficiently. It can also be used for testing Printed Circuit Board (PCB) interconnection faults.
Highlights
Dramatic improvement of integrated technology in Integrated Circuit (IC) manufacturing is rapidly leading to exceedingly complex, multi-million transistor chips
With the increase of such integration densities and complexities, problems associated with testing of ICs have become much more complex and acute[1]
It is predicted in a survey that it will soon cost more to test a transistor than to make it if current trends of increasing testing cost is maintained[2]
Summary
Dramatic improvement of integrated technology in IC manufacturing is rapidly leading to exceedingly complex, multi-million transistor chips. Deterministic test pattern enables error signals, generated due to presence of faults, and propagates them to some observable outputs from the faulty nodes or lines This method guarantees full fault coverage but the increasing densities in the circuit lead to computational complexities and the requirements of huge amount of memory to store large test data volumes. This paper introduces the design of a SoC using pseudo-random test technique to develop a cost effective IC tester. Main modules of the SoC are a micro-UART (universal asynchronous receiver and transmitter), controller unit, test Pattern Generator (PG), Buffer Register (BR), Signature Analyzer (SA) and memory modules (RAMs). FSMs generate sequence of necessary controlling pulses for loading data in the memory and executing the test process of the CUT. Enable signature analyzer for max (pi, PO, Sp) clock cycles, Set the CUT to normal mode by setting input cnm=1 ; If cnm=1 {
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