An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults

Abstract

We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIST structure contains self-enabling test pattern generators, self-configurable switch matrices, and response analyzers that all work together and reprogram themselves without any external intervention. This eliminates downloading configuration bitstreams into the FPGA after the start of testing and, hence, reduces test time. Our technique requires only six different switch matrix configurations to test the interconnect, which is fewer than prior methods, while retaining good diagnostic resolution. The area overhead to add self-configurable test structures to Xilinx FPGAs is as low as 0.5%.