Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

Abstract

This paper targets on the low power design of Memory Built In Self Test (MBIST) architecture for System on Chip (SoC) based design. Proposed address generator is developed with the blend of gray code counter and modulo counter. Bit reversing technique is adopted in this paper to generate the last pattern of gray code counter. In this work a refined architecture of MBIST is also constructed by embedding a low power address generator in it. Efficient employment of the proposed address generator in MBIST has cut-down the power consumption of BIST architecture compared to the traditional BIST. Reduction of about 6% of switching activity has been observed with novel MBIST architecture.