Design and Testing of Combinational Logic Circuits Using Built in Self Test Scheme for FPGAs

Abstract

In Very Large Scale Integration (VLSI), while manufacturing IC, Test time and cost plays a very significant role. If faulty components find during IC manufacture then cost increases. So it is essential to minimize test time and cost. In this paper Built In Self Test (BIST) architecture is designed for testing combinational logic circuits and fault models like stuck at one and stuck at zero are tested, simulated and validated using Spartan 6 FPGA and Xilinx ISE 14.2 tool. BIST architecture with fault and without fault in circuit under test is compared for the parameters such as area, memory, delays time and device utilization.