Fault-coverage analysis techniques of crosstalk in chip interconnects

Abstract

This paper addresses the problem of evaluating the effectiveness of test sets to detect crosstalk defects in system-level interconnects and buses of deep submicron (DSM) chips. The fast and accurate estimation technique will enable: 1) evaluation of different existing tests, like functional, scan, logic built-in self-test (BIST), and delay tests, for effective testing of crosstalk defects in core-to-core interconnects and 2) development of crosstalk tests if the existing tests are not sufficient, thereby minimizing the cost of interconnect testing. Based on a covering relationship we distinguish between transition tests in detecting crosstalk defects and develop an abstract crosstalk fault model for chip interconnects. With this fault model and the covering relationship, we develop a fast and efficient method to estimate the fault coverage of any general test set. We also develop a simulation-based technique to calculate the probability of occurrence of the defects corresponding to each fault, which enables the fault-coverage analysis technique to produce accurate estimates of the actual crosstalk defect coverage of a given test set. The crosstalk test and fault properties, as well as the accuracy of the proposed crosstalk coverage analysis techniques, have been validated through extensive simulation experiments. The experiments also demonstrate that the proposed crosstalk techniques are orders of magnitude faster than the alternative method of SPICE-level simulation. Finally, we demonstrate the practical applicability of the proposed fault-coverage analysis technique by using it to evaluate the crosstalk fault coverage of logic BIST tests for the system-level interconnects and buses in a digital signal processor core.