Fault-tolerant Gates Research Articles

A novel fault-tolerant multiplexer in quantum-dot cellular automata technology

Quantum-dot cellular automaton (QCA) has emerged as one of the best alternatives to CMOS technology in nanoscale. In spite of the potential advantages of QCA technology over CMOS, QCA circuits often suffer from various types of manufacturing defects and are therefore prone to fault. Hence, the design of fault-tolerant circuits in QCA technology is considered a necessity. The implementation of multiplexer circuits in QCA technology has been of great interest to researchers due to its widespread use in memory circuits and ALUs. In most of the multiplexer circuits presented in QCA, the problem of fault-tolerant is ignored. In this paper, a novel fault-tolerant three-input majority gate is initially proposed. The proposed structure has been investigated against all kinds of cell omission, extra cell deposition, and cell displacement defects. The simulation results are verified by QCA Designer 2.0.3, and it showed that it is 100, 84.98, and 100% tolerant to single-cell omission, double-cell omission, and extra cell deposition, respectively. In addition, the proposed structure shows that it is robust against cell displacement defects. Moreover, physical investigations are provided in order to confirm the function of the proposed fault-tolerant structure. Finally, using the proposed structure, a novel single-layer 2:1 multiplexer is presented. The results of comparisons indicate that the proposed designs are more reliable than the existing designs. Furthermore, QCAPro power estimator tool is employed to estimate the energy dissipation of the proposed structure.

Disjointness of Stabilizer Codes and Limitations on Fault-Tolerant Logical Gates

Stabilizer codes are a simple and successful class of quantum error-correcting codes. Yet this success comes in spite of some harsh limitations on the ability of these codes to fault-tolerantly compute. Here we introduce a new metric for these codes, the disjointness, which, roughly speaking, is the number of mostly non-overlapping representatives of any given non-trivial logical Pauli operator. We use the disjointness to prove that transversal gates on error-detecting stabilizer codes are necessarily in a finite level of the Clifford hierarchy. We also apply our techniques to topological code families to find similar bounds on the level of the hierarchy attainable by constant depth circuits, regardless of their geometric locality. For instance, we can show that symmetric 2D surface codes cannot have non-local constant depth circuits for non-Clifford gates.

A Fault-Tolerant and Efficient XOR Structure for Modular Design of Complex QCA Circuits

Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tolerant QCA XOR gates are introduced which are designed by simultaneously considering both area/delay and modular design efficiency rules. A wide range of numerical experiments are provided throughout the paper to prove the priority of the proposed gates with respect to eight other samples of the most efficient existing XOR structures, when exploiting them to build more complex circuits such as adders and error detection/correction circuits.

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.

Building topological quantum circuits: Majorana nanowire junctions

Topological quantum computation using non-Abelian Majorana zero modes localized in proximitized semiconductor nanowires requires careful electrostatic control of wire-junctions so as to manipulate and braid the zero modes enabling anyonic fault-tolerant gate operations. We theoretically investigate the topological superconducting properties of such elementary wire-junctions, the so-called T junctions, finding that the existence of the junction may nonperturbatively affect the Majorana behavior by introducing spurious non-topological subgap states mimicking zero-modes. We propose a possible solution to this potentially serious problem by showing that junctions made lithographically from two-dimensional (2D) electron gas systems may manifest robust subgap topological properties without any spurious zero modes. We propose a 2D structure that enables multiprobe tunneling experiments providing position-dependent spectroscopy, which can decisively settle outstanding open questions related to the origin of the zero-bias conductance peaks observed experimentally. We also find that junctions with trivial superconductors may result in local perturbations that induce extrinsic low-energy states similar to those associated with wire junctions.

Nonuniform code concatenation for universal fault-tolerant quantum computing

Using transversal gates is a straightforward and efficient technique for fault-tolerant quantum computing. Since transversal gates alone cannot be computationally universal, they must be combined with other approaches such as magic state distillation, code switching or code concatenation in order to achieve universality. In this paper we propose an alternative approach for universal fault-tolerant quantum computing mainly based on the code concatenation approach proposed in [PRL 112, 010505 (2014)] but in a non-uniform fashion. The proposed approach is described based on non-uniform concatenation of the 7-qubit Steane code with the 15-qubit Reed-Muller code as well as the 5-qubit code with the 15-qubit Reed-Muller code, which lead to two 49-qubit and 47-qubit codes, respectively. These codes can correct any arbitrary single physical error with the ability to perform a universal set of fault-tolerant gates, without using magic state distillation.

Optimal length of decomposition sequences composed of imperfect gates

Quantum error correcting circuitry is both a resource for correcting errors and a source for generating errors. A balance has to be struck between these two aspects. Perfect quantum gates do not exist in nature. Therefore, it is important to investigate how flaws in the quantum hardware affect quantum computing performance. We do this in two steps. First, in the presence of realistic, faulty quantum hardware, we establish how quantum error correction circuitry achieves reduction in the extent of quantum information corruption. Then, we investigate fault-tolerant gate sequence techniques that result in an approximate phase rotation gate, and establish the existence of an optimal length $$L_{\text {opt}}$$Lopt of the length L of the decomposition sequence. The existence of $$L_{\text {opt}}$$Lopt is due to the competition between the increase in gate accuracy with increasing L, but the decrease in gate performance due to the diffusive proliferation of gate errors due to faulty basis gates. We present an analytical formula for the gate fidelity as a function of L that is in satisfactory agreement with the results of our simulations and allows the determination of $$L_{\text {opt}}$$Lopt via the solution of a transcendental equation. Our result is universally applicable since gate sequence approximations also play an important role, e.g., in atomic and molecular physics and in nuclear magnetic resonance.

Concrete resource analysis of the quantum linear-system algorithm used to compute the electromagnetic scattering cross section of a 2D target

We provide a detailed estimate for the logical resource requirements of the quantum linear-system algorithm (Harrow et al. in Phys Rev Lett 103:150502, 2009) including the recently described elaborations and application to computing the electromagnetic scattering cross section of a metallic target (Clader et al. in Phys Rev Lett 110:250504, 2013). Our resource estimates are based on the standard quantum-circuit model of quantum computation; they comprise circuit width (related to parallelism), circuit depth (total number of steps), the number of qubits and ancilla qubits employed, and the overall number of elementary quantum gate operations as well as more specific gate counts for each elementary fault-tolerant gate from the standard set { X, Y, Z, H, S, T, text{ CNOT } }. In order to perform these estimates, we used an approach that combines manual analysis with automated estimates generated via the Quipper quantum programming language and compiler. Our estimates pertain to the explicit example problem size N=332{,}020{,}680 beyond which, according to a crude big-O complexity comparison, the quantum linear-system algorithm is expected to run faster than the best known classical linear-system solving algorithm. For this problem size, a desired calculation accuracy varepsilon =0.01 requires an approximate circuit width 340 and circuit depth of order 10^{25} if oracle costs are excluded, and a circuit width and circuit depth of order 10^8 and 10^{29}, respectively, if the resource requirements of oracles are included, indicating that the commonly ignored oracle resources are considerable. In addition to providing detailed logical resource estimates, it is also the purpose of this paper to demonstrate explicitly (using a fine-grained approach rather than relying on coarse big-O asymptotic approximations) how these impressively large numbers arise with an actual circuit implementation of a quantum algorithm. While our estimates may prove to be conservative as more efficient advanced quantum-computation techniques are developed, they nevertheless provide a valid baseline for research targeting a reduction of the algorithmic-level resource requirements, implying that a reduction by many orders of magnitude is necessary for the algorithm to become practical.

Gapped boundaries, group cohomology and fault-tolerant logical gates

This paper attempts to establish the connection among classifications of gapped boundaries in topological phases of matter, bosonic symmetry-protected topological (SPT) phases and fault-tolerantly implementable logical gates in quantum error-correcting codes. We begin by presenting constructions of gapped boundaries for the d-dimensional quantum double model by using d-cocycles functions (d≥2). We point out that the system supports m-dimensional excitations (m<d), which we shall call fluctuating charges, that are superpositions of point-like electric charges characterized by m-dimensional bosonic SPT wavefunctions. There exist gapped boundaries where electric charges or magnetic fluxes may not condense by themselves, but may condense only when accompanied by fluctuating charges. Magnetic fluxes and codimension-2 fluctuating charges exhibit non-trivial multi-excitation braiding statistics, involving more than two excitations. The statistical angle can be computed by taking slant products of underlying cocycle functions sequentially. We find that excitations that may condense into a gapped boundary can be characterized by trivial multi-excitation braiding statistics, generalizing the notion of the Lagrangian subgroup. As an application, we construct fault-tolerantly implementable logical gates for the d-dimensional quantum double model by using d-cocycle functions. Namely, corresponding logical gates belong to the dth level of the Clifford hierarchy, but are outside of the (d−1)th level, if cocycle functions have non-trivial sequences of slant products.

Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

Due to its ultrasmall size and extremely low power consumption, quantum-dot cellular automata (QCA) technology represents a promising alternative to semiconductor transistors at the nanoscale. Nevertheless, the design of QCA circuits is limited by their high defect rate during fabrication, making fault-tolerant QCA structures a popular research topic. The aim of this work is to design a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures. The functional results when adopting the polarization and kink energy of the proposed majority gate under such single cell and double cell deposition defects are fully investigated. Besides, a series of new fault-tolerant adders are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders, a thorough comparison versus previous adders with respect to fault tolerance, cell number, area, and delay is carried out. The results indicate that the proposed design can reach a high level of fault tolerance, and perform rather well in terms of other properties. For simulation analysis, the QCADesigner tool is used to check the functionality of all circuits.

Universal Fault-Tolerant Gates on Concatenated Stabilizer Codes

It is an oft-cited fact that no quantum code can support a set of fault-tolerant logical gates that is both universal and transversal. This no-go theorem is generally responsible for the interest in alternative universality constructions including magic state distillation. Widely overlooked, however, is the possibility of non-transversal, yet still fault-tolerant, gates that work directly on small quantum codes. Here we demonstrate precisely the existence of such gates. In particular, we show how the limits of non-transversality can be overcome by performing rounds of intermediate error-correction to create logical gates on stabilizer codes that use no ancillas other than those required for syndrome measurement. Moreover, the logical gates we construct, the most prominent examples being Toffoli and controlled-controlled-Z, often complete universal gate sets on their codes. We detail such universal constructions for the smallest quantum codes, the 5-qubit and 7-qubit codes, and then proceed to generalize the approach. One remarkable result of this generalization is that any nondegenerate stabilizer code with a complete set of fault-tolerant single-qubit Clifford gates has a universal set of fault-tolerant gates. Another is the interaction of logical qubits across different stabilizer codes, which, for instance, implies a broadly applicable method of code switching.

Thresholds for Universal Concatenated Quantum Codes.

Quantum error correction and fault tolerance make it possible to perform quantum computations in the presence of imprecision and imperfections of realistic devices. An important question is to find the noise rate at which errors can be arbitrarily suppressed. By concatenating the 7-qubit Steane and 15-qubit Reed-Muller codes, the 105-qubit code enables a universal set of fault-tolerant gates despite not all of them being transversal. Importantly, the cnot gate remains transversal in both codes, and as such has increased error protection relative to the other single qubit logical gates. We show that while the level-1 pseudothreshold for the concatenated scheme is limited by the logical Hadamard gate, the error suppression of the logical cnot gates allows for the asymptotic threshold to increase by orders of magnitude at higher levels. We establish a lower bound of 1.28×10^{-3} for the asymptotic threshold of this code, which is competitive with known concatenated models and does not rely on ancillary magic state preparation for universal computation.

Topological phases with generalized global symmetries

We present simple lattice realizations of symmetry-protected topological phases with $q$-form global symmetries where charged excitations have $q$ spatial dimensions. Specifically, we construct $d$ space-dimensional models supported on a $(d+1)$-colorable graph by using a family of unitary phase gates, known as multiqubit control-$Z$ gates in quantum information community. In our construction, charged excitations of different dimensionality may coexist and form a short-range entangled state which is protected by symmetry operators of different dimensionality. Nontriviality of proposed models, in a sense of quantum circuit complexity, is confirmed by studying protected boundary modes, gauged models, and corresponding gapped domain walls. We also comment on applications of our construction to quantum error-correcting codes, and discuss corresponding fault-tolerant logical gates.

Topological color code and symmetry-protected topological phases

We study $(d-1)$-dimensional excitations in the $d$-dimensional color code that are created by transversal application of the $R_{d}$ phase operators on connected subregions of qubits. We find that such excitations are superpositions of electric charges and can be characterized by fixed-point wavefunctions of $(d-1)$-dimensional bosonic SPT phases with $(\mathbb{Z}_{2})^{\otimes d}$ symmetry. While these SPT excitations are localized on $(d-1)$-dimensional boundaries, their creation requires operations acting on all qubits inside the boundaries, reflecting the non-triviality of emerging SPT wavefunctions. Moreover, these SPT-excitations can be physically realized as transparent gapped domain walls which exchange excitations in the color code. Namely, in the three-dimensional color code, the domain wall, associated with the transversal $R_{3}$ operator, exchanges a magnetic flux and a composite of a magnetic flux and loop-like SPT excitation, revealing rich possibilities of boundaries in higher-dimensional TQFTs. We also find that magnetic fluxes and loop-like SPT excitations exhibit non-trivial three-loop braiding statistics in three dimensions as a result of the fact that the $R_{3}$ phase operator belongs to the third-level of the Clifford hierarchy. We believe that the connection between SPT excitations, fault-tolerant logical gates and gapped domain walls, established in this paper, can be generalized to a large class of topological quantum codes and TQFTs.

Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic

Reversible circuit is of interest due to the characteristics of low energy consumption. This paper proposes a new scheme for synthesizing fault tolerant reversible circuits. A two-step method is put forward to convert an irreversible function into a parity-preserving reversible circuit. By introducing model checking for linear temporal logic, we construct a finite state machine to synthesize small reversible gates from elementary 1-qubit and 2-qubit gates, which is more automatic than the methods proposed previously. Constrains are increased so as to reduce the synthesis time in the two step method. The parity-preserving gate constructed by the two-step method has characteristics of low quantum cost because the quantum representation obtained from the counterexample for a given function in each step has the minimum quantum cost. In order to further reduce the quantum cost and decrease the synthesis time, the semi parity-preserving gates are put forward for the first time. These gates are parity-preserving when the auxiliary input is set to 0 and opposite parity when 1. Maintaining good robustness of the system in performing specific function, semi parity-preserving gate is conducive to detecting the stuck-at fault and partial gate fault in reversible circuits. The innovation of this paper is introducing the formal method to synthesis small fault tolerant gate, so as to construct the circuit with robust (semi) parity-preserving gates.

Universal transversal gates with color codes: A simplified approach

We provide a simplified, yet rigorous presentation of the ideas from Bomb\'{i}n's paper "Gauge Color Codes" [arXiv:1311.0879v3]. Our presentation is self-contained, and assumes only basic concepts from quantum error correction. We provide an explicit construction of a family of color codes in arbitrary dimensions and describe some of their crucial properties. Within this framework, we explicitly show how to transversally implement the generalized phase gate $R_n=\text{diag}(1,e^{2\pi i/2^n})$, which deviates from the method in "Gauge Color Codes", allowing an arguably simpler proof. We describe how to implement the Hadamard gate $H$ fault-tolerantly using code switching. In three dimensions, this yields, together with the transversal $CNOT$, a fault-tolerant universal gate set $\{H,CNOT,R_3\}$ without state-distillation.

Room temperature high-fidelity holonomic single-qubit gate on a solid-state spin.

At its most fundamental level, circuit-based quantum computation relies on the application of controlled phase shift operations on quantum registers. While these operations are generally compromised by noise and imperfections, quantum gates based on geometric phase shifts can provide intrinsically fault-tolerant quantum computing. Here we demonstrate the high-fidelity realization of a recently proposed fast (non-adiabatic) and universal (non-Abelian) holonomic single-qubit gate, using an individual solid-state spin qubit under ambient conditions. This fault-tolerant quantum gate provides an elegant means for achieving the fidelity threshold indispensable for implementing quantum error correction protocols. Since we employ a spin qubit associated with a nitrogen-vacancy colour centre in diamond, this system is based on integrable and scalable hardware exhibiting strong analogy to current silicon technology. This quantum gate realization is a promising step towards viable, fault-tolerant quantum computing under ambient conditions.

Fault-tolerant conversion between the Steane and Reed-Muller quantum codes.

Steane's 7-qubit quantum error-correcting code admits a set of fault-tolerant gates that generate the Clifford group, which in itself is not universal for quantum computation. The 15-qubit Reed-Muller code also does not admit a universal fault-tolerant gate set but possesses fault-tolerant T and control-control-Z gates. Combined with the Clifford group, either of these two gates generates a universal set. Here, we combine these two features by demonstrating how to fault-tolerantly convert between these two codes, providing a new method to realize universal fault-tolerant quantum computation. One interpretation of our result is that both codes correspond to the same subsystem code in different gauges. Our scheme extends to the entire family of quantum Reed-Muller codes.

Robust two-qubit gates for exchange-coupled qubits

We present composite pulse sequences that perform fault-tolerant two-qubit gate operations on exchange-only quantum dot spin qubits in various experimentally relevant geometries. We show how to perform dynamically corrected two-qubit gates in exchange-only systems with the leading hyperfine error term cancelled. These pulse sequences are constructed to conform to the realistic experimental constraint of strictly non-negative couplings. We establish that our proposed pulse sequences lead to several orders of magnitude improvement in the gate fidelity compared with their uncorrected counterparts. Together with single-qubit dynamically corrected gates, our results enable noise-resistant universal quantum operations with exchange-only qubits.

A new quantum-dot cellular automata fault-tolerant five-input majority gate

A new fault-tolerant five-input majority gate for quantum-dot cellular automata (QCA) is presented. There has been considerable research on QCA as an emerging computing scheme in the nanoscale regimes. Two main logic elements for implementation with QCA are “Majority gate” and “Inverter”. In this paper, we propose a new approach to the design of fault-tolerant five-input majority gate by considering two-dimensional arrays of QCA cells. We analyze fault-tolerance properties of such block five-input majority gate with respect to misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs are provided. Our results clearly demonstrate the redundant version of the block five-input majority gate is more robust than the standard style for this gate and its usefulness in designing arithmetic circuits.