Fault-tolerant Gates Research Articles

Instantaneous braids and Dehn twists in topologically ordered states

A defining feature of topologically ordered states of matter is the existence of locally indistinguishable states on spaces with non-trivial topology. These degenerate states form a representation of the mapping class group (MCG) of the space, which is generated by braids of defects or anyons, and by Dehn twists along non-contractible cycles. These operations can be viewed as fault-tolerant logical gates in the context of topological quantum error correcting codes and topological quantum computation. Here we show that braids and Dehn twists can in general be implemented by a constant depth quantum circuit, with a depth that is independent of code distance $d$ and system size. The circuit consists of a constant depth local quantum circuit (LQC) implementing a local geometry deformation of the quantum state, followed by a permutation on (relabelling of) the qubits. The permutation requires permuting qubits that are separated by a distance of order $d$; it can be implemented by collective classical motion of mobile qubits or as a constant depth circuit using long-range SWAP operations (with a range set by $d$) on immobile qubits. Applying these results to certain non-Abelian quantum error correcting codes demonstrates how universal logical gate sets can be implemented on encoded qubits using only constant depth unitary circuits.

Improved Fault-Tolerant Quantum Simulation of Condensed-Phase Correlated Electrons via Trotterization

Recent work has deployed linear combinations of unitaries techniques to reduce the cost of fault-tolerant quantum simulations of correlated electron models. Here, we show that one can sometimes improve upon those results with optimized implementations of Trotter-Suzuki-based product formulas. We show that low-order Trotter methods perform surprisingly well when used with phase estimation to compute relative precision quantities (e.g. energies per unit cell), as is often the goal for condensed-phase systems. In this context, simulations of the Hubbard and plane-wave electronic structure models with N<105 fermionic modes can be performed with roughly O(1) and O(N2) T complexities. We perform numerics revealing tradeoffs between the error and gate complexity of a Trotter step; e.g., we show that split-operator techniques have less Trotter error than popular alternatives. By compiling to surface code fault-tolerant gates and assuming error rates of one part per thousand, we show that one can error-correct quantum simulations of interesting, classically intractable instances with a few hundred thousand physical qubits.

Reliable coplanar full adder in quantum-dot cellular automata using five-input majority logic

Quantum-dot cellular automata (QCA) is an evolving technology to design circuits at nanometer levels. Most of the digital systems have an adder integrated in the circuit. Circuits in QCA are implemented using majority gates. Most of the existing adder designs are implemented using majority logic and exclusive-or logic. The circuits in QCA are prone to fabrication defects that can affect the performance of the circuit drastically. Missing cell defect is crucial among them. In this work, the existing gates used to implement the adders are analyzed, and a reliable clock zone full adder is proposed using the better fault tolerant gate. The proposed adder is more reliable since both the Sum and Carry are generated by reliable gates. Missing cell defect analysis and design validation are carried out using QCADesigner. The proposed design has fewer cells and more reliability compared to the designs which have considered reliability as an important factor to design adders.

A fault-tolerant non-Clifford gate for the surface code in two dimensions.

Fault-tolerant logic gates will consume a large proportion of the resources of a two-dimensional quantum computing architecture. Here we show how to perform a fault-tolerant non-Clifford gate with the surface code; a quantum error-correcting code now under intensive development. This alleviates the need for distillation or higher-dimensional components to complete a universal gate set. The operation uses both local transversal gates and code deformations over a time that scales with the size of the qubit array. An important component of the gate is a just-in-time decoder. These decoding algorithms allow us to draw upon the advantages of three-dimensional models using only a two-dimensional array of live qubits. Our gate is completed using parity checks of weight no greater than four. We therefore expect it to be amenable with near-future technology. As the gate circumvents the need for magic-state distillation, it may reduce the resource overhead of surface-code quantum computation considerably.

QCA-Based RAM Design Using a Resilient Reversible Gate with Improved Performance

Reversible logic and Quantum dot cellular automata are the prospective pillars of quantum computing. These paradigms can potentially reduce the size and power of the future chips while simultaneously maintaining the high speed. RAM cell is a crucial component of computing devices. Design of a RAM cell using a blend of reversible logic and QCA technology will surpass the limitations of conventional RAM structure. This motivates us to explore the design of a RAM cell using reversible logic in QCA framework. The performance of a reversible circuit can be improved by utilizing a resilient reversible gate. This paper presents the design of QCA-based reversible RAM cell using an efficient, fault-tolerant and low power reversible gate. Initially, a novel reversible gate is proposed and implemented in QCA. The QCA layout of the proposed reversible gate is designed using a unique multiplexer circuit. Further, a comprehensive analysis of the gate is carried out for standard Boolean functions, cost function and power dissipation and it has been found that the proposed gate is 75.43% more cost-effective and 58.54% more energy-efficient than the existing reversible gates. To prove the inherent testability of the proposed gate, its rigorous testing is carried out against various faults and the proposed gate is found to be 69.2% fault-tolerant. For all the performance parameters, the proposed gate has performed considerably better than the existing ones. Furthermore, the proposed gate is explicitly used for designing reversible D latch and RAM cell, which are crucial modules of sequential logic circuits. The proposed latch is 45.4% more cost effective than the formerly reported D latch. The design of QCA-based RAM cell using reversible logic is novel and not reported earlier in the literature.

The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate

Inverter and majority gates are considered as two important primitive gates for designing logical circuits in the quantum-dot cellular automata (QCA) technology. Up to now, many QCA layouts have been introduced for three-input majority gates, most of which are not robust against the QCA defects and so they are prone to faults. In this paper, we propose an efficient fault-tolerant 3-input majority gate with ten simple and rotated cells whose output signal strength is very high (± 9.93e−001). The fault tolerance of the proposed structure is investigated against cell omission, extra-cell deposition, and displacement defects. The results show that the proposed structure is 100% and 90% tolerant against single-cell omission and extra-cell deposition defects. Moreover, the error probability of the proposed gate under cell omission and extra-cell deposition defects is investigated through analytical modeling. Using the proposed fault-tolerant structure, two basic circuits including a fault-tolerant QCA full-adder and a fault-tolerant 2:1 QCA multiplexer are introduced. Finally, using the proposed circuits, a fault-tolerant one-bit arithmetic logic unit with four mathematical and logical operations is designed and implemented. To verify the proposed three-input majority gate, some physical proofs are provided. The results of simulations by QCADesigner 2.0.3 show that the proposed circuits work well. The power analysis of the proposed structure is performed using a QCAPro tool. The comparison results show that the proposed circuits are much better than the previous designs.

Triangular color codes on trivalent graphs with flag qubits

The color code is a topological quantum error-correcting code supporting a variety of valuable fault-tolerant logical gates. Its two-dimensional version, the triangular color code, may soon be realized with currently available superconducting hardware despite constrained qubit connectivity. To guide this experimental effort, we study the storage threshold of the triangular color code against circuit-level depolarizing noise. First, we adapt the Restriction Decoder to the setting of the triangular color code and to phenomenological noise. Then, we propose a fault-tolerant implementation of the stabilizer measurement circuits, which incorporates flag qubits. We show how information from flag qubits can be used in an efficient and scalable way with the Restriction Decoder to maintain the effective distance of the code. We numerically estimate the threshold of the triangular color code to be 0.2%, which is competitive with the thresholds of other topological quantum codes. We also prove that 1-flag stabilizer measurement circuits are sufficient to preserve the full code distance, which may be used to find simpler syndrome extraction circuits of the color code.

An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata

This paper proposes a novel fault-tolerant 5-input majority gate using 28 simple and rotated cells in Quantum-dot Cellular Automata (QCA) technology. The proposed gate is evaluated against cell omission, extra-cell deposition, and cell displacement defects to check the stability. The simulation results using QCADesigner 2.0.3 software show that the proposed gate is 59% and 100% fault-tolerant against single-cell omission and extra-cell deposition defects, respectively. It also shows good tolerance against cell displacement defects. Moreover, the functionality of the proposed structure is confirmed by physical proofs. QCAPro tool is used to analyze the power consumption of the proposed structure. Fault-tolerant versions of basic gates including 2-input AND, 2-input XOR, and 3-input XOR are suggested using the proposed gate. Moreover, a fault-tolerant 2:1 multiplexer, a 4-bit even parity generator, and an Arithmetic Logic Unit (ALU) are developed and implemented using the proposed fault-tolerant basic gates.

Gate-Error-Resilient Quantum Steane Codes

An encoderless quantum code is capable of connecting quantum information by replacing the encoder circuit with a fault-tolerant single-qubit gate arrangement. As a further benefit, in contrast to state preparation techniques, our encoderless scheme requires no prior knowledge of the input information, therefore totally unknown states can be encoded fault-tolerantly. Our encoderless quantum code delivers a frame error rate that is three orders of magnitude lower than that of the corresponding scheme relying on a non-fault-tolerant encoder, when the gate error probability is as high as 10−3.

Robust scalable architecture for a hybrid spin-mechanical quantum entanglement system

Practical quantum information technique requires a large scalable quantum network. We proposed a hybrid system for deterministic scalable spin entanglement network based on nitrogen-vacancy (NV) centers in diamond coupling with carbon nanotube. The fault-tolerant entangled gate between two remote NV centers can be realized with vibrating nanotube assisted spin-spin interaction with current experimental technology. This interaction can be directly generalized to multi-NV-center entanglement architecture. Moreover, the effects of the single spin dephasing (SSD) and spin cross relaxation (SCR) on this state generation process were analyzed in detail. We found that the decay rate scales as ${N}^{2}$, corresponding to the number of independent decoherence channels. However, by employing dressed state protection and independent tunable interaction method, SSD and SCR can be mitigated efficiently and the decay rate of the generated multi-NV-center entanglement scales as $N$, which boosts the size of the entanglement network up to hundreds of qubits. Such a hybrid quantum system compatible with current topological protection provides a useful platform for the investigation of quantum computation.

Design of integrated reversible fault-tolerant arithmetic and logic unit

In recent years, design of low power high-speed nano computing systems have drawn more attention. Reversible Logic is a technique popularly used to design the computing systems to achive them. In a computer, the arithmetic logic unit (ALU) is the fundamental computing module. In this paper, a novel Reversible Arithmetic and Logic Unit is proposed, where a single module performs both arithmetic and logical operations. The possible arithmetic operation includes transfer, addition with carry, subtract, complement and increment. The possible logical operations are AND, OR, XOR, COPY and CONSTANT. The control signal is a key element which defines and alters the data path in order to produce either arithmetic or logical output. The fault-tolerant KMD gates are utilized to construct the ALU. Here, two approaches are discussed for the construction of ALU. In the first approach, ALU is constructed using KMD gates only, whereas in the second approach, combination of KMD, Toffoli and Fredkin gates are used. The functional realization is performed in Quantum Cellular Automata. Quantum circuit is also derived for the same. The obtained results are evident for the improved Quantum cost up to 69%, Constant input up to 40% and Number of gates up to 21% compared to the existing designs.

Fault-tolerant magic state preparation with flag qubits

Magic state distillation is one of the leading candidates for implementing universal fault-tolerant logical gates. However, the distillation circuits themselves are not fault-tolerant, so there is additional cost to first implement encoded Clifford gates with negligible error. In this paper we present a scheme to fault-tolerantly and directly prepare magic states using flag qubits. One of these schemes requires only three ancilla qubits, even with noisy Clifford gates. We compare the physical qubit and gate cost of our scheme to the magic state distillation protocol of Meier, Eastin, and Knill (MEK), which is efficient and uses a small stabilizer circuit. For low enough noise rates, we show that in some regimes the overhead can be improved by several orders of magnitude compared to the MEK scheme which uses Clifford operations encoded in the codes considered in this work.

A novel design of fault-tolerant RAM cell in quantum-dot cellular automata with physical verification

Quantum-dot cellular automata (QCA) emerged as a viable alternative to CMOS technology in nanotechnology. Despite the potential advantages of QCA compared with CMOS technology, QCA circuits often suffer from various manufacturing defects such as cell omission, cell displacement, and extra-cell deposition, which make them unreliable and fault-prone. Hence, it is essential in QCA technology to design a fault-tolerant circuit. The design of an optimized, high-speed RAM memory has received increasing attention of researchers as the memory unit is an essential component in the digital systems. In this paper, a new design of a fault-tolerant RAM cell is introduced using two proposed fault-tolerant three- and five-input majority gates. The proposed fault-tolerant majority gates have been evaluated in the presence of variety of defects such as cell omission, cell displacement and extra-cell deposition. The QCADesigner 2.0.3 and QCAPro tools are used for our simulations. The results indicate that the proposed majority gates have less energy consumption and more fault tolerance in comparison with the previous works. Furthermore, some physical calculations are presented to assess the functionality of the proposed gates.

Fault-Tolerant Logical Gates in the IBM Quantum Experience.

Quantum computers will require encoding of quantum information to protect them from noise. Fault-tolerant quantum computing architectures illustrate how this might be done but have not yet shown a conclusive practical advantage. Here we demonstrate that a small but useful error detecting code improves the fidelity of the fault-tolerant gates implemented in the code space as compared to the fidelity of physically equivalent gates implemented on physical qubits. By running a randomized benchmarking protocol in the logical code space of the [4,2,2] code, we observe an order of magnitude improvement in the infidelity of the gates, with the two-qubit infidelity dropping from 5.8(2)% to 0.60(3)%. Our results are consistent with fault-tolerance theory and conclusively demonstrate the benefit of carrying out computation in a code space that can detect errors. Although the fault-tolerant gates offer an impressive improvement in fidelity, the computation as a whole is not below the fault-tolerance threshold because of noise associated with state preparation and measurement on this device.

Fault-tolerant gates via homological product codes

A method for the implementation of a universal set of fault-tolerant logical gates is presented using homological product codes. In particular, it is shown that one can fault-tolerantly map between different encoded representations of a given logical state, enabling the application of different classes of transversal gates belonging to the underlying quantum codes. This allows for the circumvention of no-go results pertaining to universal sets of transversal gates and provides a general scheme for fault-tolerant computation while keeping the stabilizer generators of the code sparse.

New designs of fault-tolerant adders in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has attracted attention as one of the best forms of alternative Nanoscale CMOS technology. It has facilitated the designing of digital circuits with high density and speed. One of the important issues in QCA technology is designing fault-tolerant digital circuits. QCA-based circuits frequently suffer from fabrication and unstable faults: these make them unreliable and susceptible to breakdown. In this paper, two new fault-tolerant 3-input majority gates have been proposed in QCA technology. The robustness of the proposed structures has been evaluated in terms of defects such as cell omission, deposition of extra cell and cell displacement defects. The simulations were performed using the QCA Designer 2.0.03 and QCAPro tools to measure performance and energy consumption. The obtained results indicate that the proposed structures benefit from higher fault-tolerant in comparison to previous designs. Moreover, we provided four new fault-tolerant full-adders and a multi-bit adder using the proposed structures and acceptable results are archived.

Low overhead Clifford gates from joint measurements in surface, color, and hyperbolic codes

One of the most promising routes towards fault-tolerant quantum computation utilizes topological quantum error correcting codes, such as the $\mathbb{Z}_2$ surface code. Logical qubits can be encoded in a variety of ways in the surface code, based on either boundary defects, holes, or bulk twist defects. However proposed fault-tolerant implementations of the Clifford group in these schemes are limited and often require unnecessary overhead. For example, the Clifford phase gate in certain planar and hole encodings has been proposed to be implemented using costly state injection and distillation protocols. In this paper, we show that within any encoding scheme for the logical qubits, we can fault-tolerantly implement the full Clifford group by using joint measurements involving a single appropriately encoded logical ancilla. This allows us to provide new low overhead implementations of the full Clifford group in surface and color codes. It also provides the first proposed implementations of the full Clifford group in hyperbolic codes. We further use our methods to propose state-of-the art encoding schemes for small numbers of logical qubits; for example, for code distances $d = 3,5,7$, we propose a scheme using $60, 160, 308$ (respectively) physical data qubits, which allow for the full logical Clifford group to be implemented on two logical qubits. To our knowledge, this is the optimal proposal to date, and thus may be useful for demonstration of fault-tolerant logical gates in small near-term quantum computers.

Encoding Electronic Spectra in Quantum Circuits with Linear T Complexity

We construct quantum circuits which exactly encode the spectra of correlated electron models up to errors from rotation synthesis. By invoking these circuits as oracles within the recently introduced "qubitization" framework, one can use quantum phase estimation to sample states in the Hamiltonian eigenbasis with optimal query complexity $O(\lambda / \epsilon)$ where $\lambda$ is an absolute sum of Hamiltonian coefficients and $\epsilon$ is target precision. For both the Hubbard model and electronic structure Hamiltonian in a second quantized basis diagonalizing the Coulomb operator, our circuits have T gate complexity $O({N + \log (1/\epsilon}))$ where $N$ is number of orbitals in the basis. This enables sampling in the eigenbasis of electronic structure Hamiltonians with T complexity $O(N^3 /\epsilon + N^2 \log(1/\epsilon)/\epsilon)$. Compared to prior approaches, our algorithms are asymptotically more efficient in gate complexity and require fewer T gates near the classically intractable regime. Compiling to surface code fault-tolerant gates and assuming per gate error rates of one part in a thousand reveals that one can error correct phase estimation on interesting instances of these problems beyond the current capabilities of classical methods using only about a million superconducting qubits in a matter of hours.

Real Randomized Benchmarking

Randomized benchmarking provides a tool for obtaining precise quantitative estimates of the average error rate of a physical quantum channel. Here we define real randomized benchmarking, which enables a separate determination of the average error rate in the real and complex parts of the channel. This provides more fine-grained information about average error rates with approximately the same cost as the standard protocol. The protocol requires only averaging over the real Clifford group, a subgroup of the full complex Clifford group, and makes use of the fact that it forms an orthogonal 2-design. It therefore allows benchmarking of fault-tolerant gates for an encoding which does not contain the full Clifford group transversally. Furthermore, our results are especially useful when considering quantum computations on rebits (or real encodings of complex computations), in which case the real Clifford group now plays the role of the complex Clifford group when studying stabilizer circuits.

Design and comparison of new fault-tolerant majority gate based on quantum-dot cellular automata * * Project supported by the National Natural Science Foundation of China (No. 61271122).

Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.