Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

Abstract

Due to its ultrasmall size and extremely low power consumption, quantum-dot cellular automata (QCA) technology represents a promising alternative to semiconductor transistors at the nanoscale. Nevertheless, the design of QCA circuits is limited by their high defect rate during fabrication, making fault-tolerant QCA structures a popular research topic. The aim of this work is to design a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures. The functional results when adopting the polarization and kink energy of the proposed majority gate under such single cell and double cell deposition defects are fully investigated. Besides, a series of new fault-tolerant adders are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders, a thorough comparison versus previous adders with respect to fault tolerance, cell number, area, and delay is carried out. The results indicate that the proposed design can reach a high level of fault tolerance, and perform rather well in terms of other properties. For simulation analysis, the QCADesigner tool is used to check the functionality of all circuits.