Towards nanoscale fault-tolerant logical circuits using proposed robust majority voter in quantum-dot cellular automata technology

Abstract

The occupied area, power consumption, and delay are the most crucial and critical factors in constructing integrated circuits. Due to the reduced occupied area, highly low power consumption, and extremely high speed of quantum-dot cellular automata (QCA) technology, it is one of the finest alternatives to complementary metal–oxide–semiconductor (CMOS) technology for nanoscale construction of circuits. On the other hand, fault tolerance becomes crucial in QCA due to the inherent sensitivity of quantum dots to various sources of errors and faults. These errors can arise from environmental disturbances, manufacturing imperfections, thermal fluctuations, and other factors. The presence of defects or faults can significantly impact the functionality and accuracy of QCA systems, leading to incorrect computation or signal corruption. To address these challenges, fault-tolerant structures are designed in QCA systems. These structures are specifically engineered to detect, tolerate, and mitigate the effects of faults, thereby enhancing the reliability and robustness of QCA-based computation. Fault-tolerant designs aim to ensure that the system can continue to operate correctly even in the presence of defects or faults. In QCA, proposed a fault-tolerant majority gate is necessary to ensure reliable computation in the presence of defects or faults. The fault-tolerant majority gate is a fundamental component in digital logic circuits, and it plays a crucial role in performing computations. It takes multiple input signals and produces an output based on the majority of those inputs. In classical computing, the majority gates are typically implemented using transistors. Therefore, this paper introduces a new and efficient fault-tolerant 3-input majority voter (FT MV3) using 11 simple and rotated cells in the QCA technology, which is 100% and 90.47% tolerant against single-cell and double-cell omission defects. The recommended FT MV3 gate verification is confirmed using some physical proofs. Afterward, to illustrate the performance of the introduced gate, three fault-tolerant computational circuits, including multiplexer, adder and ALU, are presented using the introduced FT MV3 gate. The comparison of the proposed fault tolerant ALU to the best coplanar design shows a 28.80% and 34.01% reduction of cell count and occupied area, respectively. All circuits are simulated using QCADesigner 2.0.3 software.