Fast Design Space Exploration Research Articles

Optimizing code allocation for hybrid on-chip memory in IoT systems

With the increasing application of IoT devices, the memory subsystem, as the performance and energy bottleneck of IoT systems, has received a lot of attention. One of the keys is on-chip memory which can bridge the performance gap between the CPU and main memory. While many off-the-shelf embedded processors utilize the hybrid on-chip memory architecture containing scratchpad memories (SPMs) and caches, most existing literature ignores the collaboration between caches and SPMs. This paper proposes static SPM allocation strategies for the architecture mentioned above in IoT systems, which try to minimize the overall instruction memory subsystem latency and/or energy consumption. We capture the intra- and inter-task cache conflict misses via a fine-grained temporal cache behavior model. Based on this cache conflict information, we propose an integer linear programming (ILP) algorithm to generate an optimal static function level SPM allocation for system performance. Furthermore, to improve the scalability of the proposed allocation scheme for an enormous task set, we offer the interference factor to calculate the interference impact quantitatively. Then, based on the interference factor, we present two approximate knapsack based heuristic algorithms to provide near optimal static allocation schemes at both function- and basic block-level granularities, which favors fast design space exploration. The experiment results demonstrate that the proposed solution achieves a 30.85% improvement in memory performance, and up to 31.39% reduction in energy consumption, compared to the existing SPM allocation scheme at the function level. In addition, the proposed basic block level allocation algorithm shows better performance than our function level allocation algorithm and other basic block level allocation algorithm.

Fast and Scalable Design Space Exploration for Deep Learning on Embedded Systems

Fast and Scalable Design Space Exploration for Deep Learning on Embedded Systems

Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue

High-Level Synthesis (HLS) has multiple significant advantages over traditional RT-level design flows. One in particular that we address in this work is the ability to generate multiple functional equivalent design variants with unique trade-offs like area, performance and power from the same behavioral description. This is typically done by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers), loops (unroll, partially unroll, no unroll or pipeline) and functions (inline or not). Setting different pragma combinations lead to these different design implementations. Out of all the pragma combinations the designer is typically only interested in those that lead to the Pareto-optimal designs. Fortunately, this search can be automated, but unfortunately, the search space to find these pragma combinations grows supra-linearly with the number of pragma settings. Thus, fast and efficient heuristics are needed. These heuristics generate a new pragma combination and then evaluate their effect by synthesizing (HLS) it. The most time-consuming part of this process is having to execute a full synthesis (HLS) on the behavioral description for every new pragma combination. One obvious way to accelerate the exploration is to parallelize the exploration process using a multithreaded heuristic. The theoretical speedup should match the number of parallel threads. The main problem with this approach is that every HLS invokation requires to check out a HLS tool license. This license is not released until the synthesis process has finished. This implies that the maximum number of parallel threads is restricted by the number of available licenses, which in the ASIC case are extremely expensive. On the contrary, FPGA vendors make their HLS tools free. Thus, it is tempting to investigate if FPGA HLS tools can be used to find the Pareto-optimal designs in the ASIC case. To address this, in this work we present a dedicated multithreaded parallel HLS design space explorer (DSE) based on transfer learning that is able to accelerate HLS DSE for ASICs by targeting first FPGAs and using machine learning to convert the exploration results obtained to find the optimal ASIC equivalent. Experimental results show the effectiveness and robustness of our approach.

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.

Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis

In this paper, we present a machine learning based High-Level Synthesis (HLS) design space explorer (DSE) that significantly reduces the exploration runtime while leading to very accurate results. In order to do so, we leverage the power of low level virtual machine (LLVM) to generate the features used in the machine learning (ML) model. The proposed design space explorer uses a modified version of simulated annealing (SA) algorithm, where initially the search space is sampled to generate the predictive model. In this work we used gradient boost regression algorithm as our preferred ML model and achieve comparable results as a full DSE that performs logic synthesis for each newly generated design.

Fast Design Space Exploration of Nonlinear Systems: Part II

Nonlinear system design is often a multiobjective optimization problem involving the search for a design that satisfies a number of predefined constraints. The design space is typically very large since it includes all possible system architectures with different combinations of components composing each architecture. In this article, we address nonlinear system design space exploration through a two-step approach encapsulated in a framework called fast design space exploration of nonlinear systems (ASSENT). In the first step, we use a genetic algorithm to search for system architectures that allow discrete choices for component values or else only component values for a fixed architecture. This step yields a coarse design since the system may or may not meet the target specifications. In contrast to prior works on design space exploration that rely on forward design, we use an inverse design in step 2 to search over a continuous space and fine-tune the component values with the goal of improving the value of the objective function. We use a neural network (NN) to model the system response. The NN is converted into a mixed-integer linear program for active learning to sample component values efficiently. We illustrate the efficacy of ASSENT on problems ranging from nonlinear system design to the design of electrical circuits. Experimental results show that ASSENT achieves the same or better value of the objective function compared to various other optimization techniques for nonlinear system design by up to 53%. We improve sample efficiency by 6– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12\times $ </tex-math></inline-formula> compared to reinforcement learning-based synthesis of electrical circuits.

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators

Analog In-Memory Compute (AIMC) arrays can store weights and perform matrix-vector multiplication operations for Deep Convolutional Neural Networks (CNNs). A number of recent efforts have integrated AIMC arrays into hybrid digital-analog accelerators in a multi-layer parallel manner to achieve energy efficiency and high throughput. Multi-layer parallelism on large-scale tile-based architectures need efficient mapping support at the processing element (PE)-level ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e.g.</i> , digital or analog processing elements) and tile-level. To find the most efficient architectures, fast and accurate design space exploration (DSE) support is required. In this paper, a novel DSE framework, AERO, is presented to characterize a CNN inference workload executing on hybrid tile-based architectures that supports multi-layer parallelism. Three characteristics can be seen in our DSE framework: (1) It presents a hierarchical Tile/PE-level mapping exploration strategy including inter-layer interaction, and allowing layer fusion/splitting configurations for PE-level mapping optimization. (2) It unlocks different Performance, Power and Area (PPA) exploration points under both sufficient and limited resource constraints, while limited resource case is not considered in prior works of multi-layer parallel architectures. The impact of weight loading and weight stationary mapping are analyzed for better insights into hybrid tile-based architectures. (3) It incorporates a detailed PPA model that supports a broad range of hybrid digital and analog units in a tile. Experimental case-studies are performed for realistic and relevant benchmarks such as MLP, CNNs (Lenet-5, Resnet-18,-34,-50 and −101).

Knowledge-Based Neural Networks for Fast Design Space Exploration of Hybrid Copper-Graphene On-Chip Interconnect Networks

In this article, an artificial neural network (ANN) is developed in order to predict the per-unit-length (p. u. l.) parameters of hybrid copper-graphene on-chip interconnects from a prior knowledge of their structural geometry and layout. The salient feature of the proposed ANN is that it combines knowledge of the p. u. l. parameters extracted from empirical models along with that extracted from a rigorous full-wave electromagnetic solver. As a result, the proposed ANN is referred to as a knowledge-based neural network (KBNN). The KBNN has been found to converge to the same accuracy as a conventional ANN but at the expense of far smaller training time costs. As a result, the KBNN is much more suitable for performing design space explorations.

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.

Compute-in-memory (CIM) is an attractive solution to process the extensive workloads of multiply-and-accumulate (MAC) operations in deep neural network (DNN) hardware accelerators. A simulator with options of various mainstream and emerging memory technologies, architectures, and networks can be a great convenience for fast early-stage design space exploration of CIM hardware accelerators. DNN+NeuroSim is an integrated benchmark framework supporting flexible and hierarchical CIM array design options from a device level, to a circuit level and up to an algorithm level. In this study, we validate and calibrate the prediction of NeuroSim against a 40-nm RRAM-based CIM macro post-layout simulations. First, the parameters of a memory device and CMOS transistor are extracted from the foundry’s process design kit (PDK) and employed in the NeuroSim settings; the peripheral modules and operating dataflow are also configured to be the same as the actual chip implementation. Next, the area, critical path, and energy consumption values from the SPICE simulations at the module level are compared with those from NeuroSim. Some adjustment factors are introduced to account for transistor sizing and wiring area in the layout, gate switching activity, post-layout performance drop, etc. We show that the prediction from NeuroSim is precise with chip-level error under 1% after the calibration. Finally, the system-level performance benchmark is conducted with various device technologies and compared with the results before the validation. The general conclusions stay the same after the validation, but the performance degrades slightly due to the post-layout calibration.

The Paramak: automated parametric geometry construction for fusion reactor designs.

During the conceptual design process of fusion reactors it is useful to rapidly prototype different design concepts and assess their suitability against a range of high level requirements. Rapid prototyping allows the 'fail early' mantra of other fields to be applied to engineering design. Furthermore, the rapid generation of low fidelity analysis allows fast exploration of design space, which enables better decisions to be made during concept selection and the detailed design phase. The Paramak is an open-source tool that aims to provide automated parameter driven 3D CAD models for fusion reactor components and magnetic fusion reactors. The geometry produced is compatible with several analysis workflows and this allows iterative automated model building and analysis to help steer the design concept optimisation process. The Paramak uses CadQuery 2 to create the 3D CAD model. The Paramak framework is used to create a few example reactor configurations including: a spherical reactor, a regular large radius tokamak and a compact submersion tank reactor. Input parameters for the various reactors that the Paramak can generate generally fall into three categories: continuous ranges such as blanket thickness, integer ranges such as number of toroidal field coils and categorical parameters such as type of divertor. The Paramak facilitates parameter studies where users can investigate the impact of input design parameters on the reactor performance. The use of modern software practices allows the geometry to be continuously tested in analysis workflows to ensure it is fit for purpose. The generation of output metrics from input parameters lends itself to the use of data science and machine learning approaches in order to steer the design. The Paramak provides rapid construction of analysis ready CAD in a manner that allows the designer to save time when exploring the design space for design studies and facilitate automated generative design.

The Paramak: automated parametric geometry construction for fusion reactor designs.

During the conceptual design process of fusion reactors it is useful to rapidly prototype different design concepts and assess their suitability against a range of high level requirements. Rapid prototyping allows the 'fail early' mantra of other fields to be applied to engineering design. Furthermore, the rapid generation of low fidelity analysis allows fast exploration of design space, which enables better decisions to be made during concept selection and the detailed design phase. The Paramak is an open-source tool that aims to provide automated parameter driven 3D CAD models for fusion reactor components and magnetic fusion reactors. The geometry produced is compatible with several analysis workflows and this allows iterative automated model building and analysis to help steer the design concept optimisation process. The Paramak uses CadQuery 2 to create the 3D CAD model. The Paramak framework is used to create a few example reactor configurations including: a spherical reactor, a regular large radius tokamak and a compact submersion tank reactor. Input parameters for the various reactors that the Paramak can generate generally fall into three categories: continuous ranges such as blanket thickness, integer ranges such as number of toroidal field coils and categorical parameters such as type of divertor. The Paramak facilitates parameter studies where users can investigate the impact of input design parameters on the reactor performance. The use of modern software practices allows the geometry to be continuously tested in analysis workflows to ensure it is fit for purpose. The generation of output metrics from input parameters lends itself to the use of data science and machine learning approaches in order to steer the design. The Paramak provides rapid construction of analysis ready CAD in a manner that allows the designer to save time when exploring the design space for design studies and facilitate automated generative design.

Compact Thermal Modelling Tool for Fast Design Space Exploration of 3D ICs with Integrated Microchannels

Integrated microchannel cooling is a very promising concept for thermal management of 3D ICs, because it offers much higher cooling performance than conventional forced-air convection. The thermo-fluidic simulations of such chips are usually performed using a computational fluid dynamics (CFD) approach. However, due to the complexity of the fluid flow modelling, such simulations are typically very long and faster models are therefore considered. This paper demonstrates the advantages of TIMiTIC—a compact thermal simulator for chips with liquid cooling—and shows its practical usefulness in design space exploration of 3D ICs with integrated microchannels. Moreover, thermal simulations of a 3D processor model using the proposed tool are used to estimate the optimal power dissipation profile in the chip and to prove that such an optimal profile allows for a very significant (more than 10 °C) peak temperature reduction. Finally, a custom correlation metric is introduced which allows the comparison of the power distribution profiles in terms of the peak chip temperature that they produce. Statistical analysis of the simulation results demonstrates that this metric is very accurate and can be used for example in thermal-aware task scheduling or dynamic voltage and frequency scaling (DVFS) algorithms.

Machine learning for nonintrusive model order reduction of the parametric inviscid transonic flow past an airfoil

Fluid flow in the transonic regime finds relevance in aerospace engineering, particularly in the design of commercial air transportation vehicles. Computational fluid dynamics models of transonic flow for aerospace applications are computationally expensive to solve because of the high degrees of freedom as well as the coupled nature of the conservation laws. While these issues pose a bottleneck for the use of such models in aerospace design, computational costs can be significantly minimized by constructing special, structure-preserving surrogate models called reduced-order models. In this work, we propose a machine learning method to construct reduced-order models via deep neural networks and we demonstrate its ability to preserve accuracy with a significantly lower computational cost. In addition, our machine learning methodology is physics-informed and constrained through the utilization of an interpretable encoding by way of proper orthogonal decomposition. Application to the inviscid transonic flow past the RAE2822 airfoil under varying freestream Mach numbers and angles of attack, as well as airfoil shape parameters with a deforming mesh, shows that the proposed approach adapts to high-dimensional parameter variation well. Notably, the proposed framework precludes the knowledge of numerical operators utilized in the data generation phase, thereby demonstrating its potential utility in the fast exploration of design space for diverse engineering applications. Comparison against a projection-based nonintrusive model order reduction method demonstrates that the proposed approach produces comparable accuracy and yet is orders of magnitude computationally cheap to evaluate, despite being agnostic to the physics of the problem.

High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems

Compared to traditional hardware development methodologies, high-level synthesis (HLS) offers a faster time-to-market and lower design-cost at the expense of implementation efficiency. Although HLS tools are becoming popular in some applications, such as digital signal processing and neural network classification, their usability on cryptographic applications is largely unexplored. This feasibility is critical especially for cryptosystems that are under development, such as the next-generation public-key cryptosystems needed for quantum-resistance. This letter provides a thorough investigation of HLS on number theoretic transform (NTT)-the core arithmetic function of lattice-based quantum-resistant cryptosystems. We demonstrate a fast yet extensive design space exploration of NTT through the Vivado HLS tool, analyze the shortcomings/challenges of optimized configurations, and quantitatively compare the results to software-based and hand-coded hardware designs.

A comparison study of two multifidelity methods for aerodynamic optimization

Industrial aerodynamic design applications require multiobjective optimization tools able to provide design feedback to the engineers. This is true especially when optimization studies are carried out during the conceptual design stage. The need for fast optimization methods has led to the development of multifidelity methods in a surrogate based optimization environment. Multifidelity tools have the potential to accelerate the design process, primarily due to the lower cost associated with the low fidelity tool. In addition to this, the design stage is shortened as mature and reliable high fidelity design information is provided earlier in the design cycle. Despite this high potential of these methods, there is no explicit comparison available in the literature between multifidelity surrogate based optimization tools for industrial aerodynamic problems. This paper aims at providing a direct comparison between two multiobjective multifidelity surrogate based optimization methods developed by our group. The first approach uses a trust region formulation for efficient multiobjective that does not require gradients. The second is using the concept of expected improvement to perform fast design space exploration based on a novel Kriging modification for multifidelity data. The tools are applied in two aerodynamic design problems: optimization of a high lift configuration in respect to maximum lift maximization and an airfoil design for transonic cruising conditions. These problems feature characteristics of industrial interest. They involve difficult physical analyses in the case of the high lift configuration and a more complex optimization formulation due to the increased dimensionality in the case of the transonic airfoil. Our presented methods are compared against a CFD-based optimization, a surrogate based optimization using only high fidelity data and a multifidelity surrogate based optimization based on Co-Kriging. Early results suggest that the trust region method can quickly provide improved designs leading to an efficient Pareto front. The expected improvement based method shows fast exploration attributes and a wide Pareto front.

Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

In recent years, convolutional neural networks (CNNs) have become widely adopted for computer vision tasks. Field-programmable gate arrays (FPGAs) have been adequately explored as a promising hardware accelerator for CNNs due to its high performance, energy efficiency, and reconfigurability. However, prior FPGA solutions based on the conventional convolutional algorithm is often bounded by the computational capability of FPGAs (e.g., the number of DSPs). To address this problem, the feature maps are transformed to a special domain using fast algorithms to reduce the arithmetic complexity. Winograd and fast Fourier transformation (FFT), as fast algorithm representatives, first transform input data and filter to Winograd or frequency domain, then perform element-wise multiplication, and apply inverse transformation to get the final output. In this paper, we propose a novel architecture for implementing fast algorithms on FPGAs. Our design employs line buffer structure to effectively reuse the feature map data among different tiles. We also effectively pipeline the Winograd/FFT processing element (PE) engine and initiate multiple PEs through parallelization. Meanwhile, there exists a complex design space to explore. We propose an analytical model to predict the resource usage and the performance. Then, we use the model to guide a fast design space exploration. Experiments using the state-of-the-art CNNs demonstrate the best performance and energy efficiency on FPGAs. We achieve 854.6 and 2479.6 GOP/s for AlexNet and VGG16 on Xilinx ZCU102 platform using Winograd. We achieve 130.4 GOP/s for Resnet using Winograd and 201.1 GOP/s for YOLO using FFT on Xilinx ZC706 platform.

HAPE: A high-level area-power estimation framework for FPGA-based accelerators

Recent embedded applications are widely used in several industrial domains such as automotive and multimedia systems. These applications are critical and complex, involving more computing resources and therefore increasing the power consumption of the system. Although performance still remains an important design metric, power consumption has become a critical factor for several systems, particularly after the increasing complexity of recent System-on-Chip (SoC) designs. Consequently, the whole computing domain is being forced to switch from a focus on high performance computation to energy-efficient computation. In addition to the time-to-market challenge, designers need to estimate, rapidly and accurately, both area occupation and power consumption of complex and diverse applications. High-Level Synthesis (HLS) has been emerged as an attractive solution for designers to address this challenge in order to explore a large number of design points at a high-level of abstraction. In this paper, we target FPGA-based accelerators. We propose HAPE, a high-level framework based on analytic models for area and power estimation without requiring register-transfer level (RTL) implementations. This technique allows to estimate the required FPGA resources and the power consumption at the source code level. The proposed models also enable a fast design space exploration (DSE) with different trade-offs through HLS optimization pragmas, including loop unrolling, pipelining, array partitioning, etc. The accuracy of our proposed models is evaluated by using a variety of synthetic benchmarks. Estimated power results are compared to real board measurements. The area and power estimation results are less than 5% of error compared to RTL implementations.

Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip

To fully exploit the massive parallelism of many-core on a chip, this work tackles the problem of mapping large-scale applications onto heterogeneous networks-on-chip (NoCs) while minimizing hotspots. A task-resource co-optimization framework is proposed which configures the on-chip communication infrastructure and maps the applications simultaneously and coherently, aiming to minimize the peak energy under the constraints of computation power, communication capacity, and total cost budget of on-chip resources. The problem is first formulated into a linear programming model to search for optimal solution. A heuristic is further developed for fast design space exploration at design-time and run-time in large-scale NoCs. Extensive simulations are carried out under real-world benchmarks and randomly generated task graphs to demonstrate the effectiveness and efficiency of the proposed schemes. Real system simulations show the significant improvement (30–200%) in NoCs latency and throughput compared to the state-of-the-art minimum-path approach because of the diminishing hotspots and balanced load distribution.

Design Space Exploration of Microring Resonators in Silicon Photonic Interconnects: Impact of the Ring Curvature

A detailed analysis of fundamental tradeoffs between ring radius and coupling gap size is presented to draw realistic borders of the possible design space for microring resonators (MRRs). The coupling coefficient for the ring-waveguide structure is estimated based on an integration of the nonuniform gap between the ring and the waveguide. Combined with the supermode analysis of two coupled waveguides, this approach is further expanded into a closed-form equation that describes the coupling strength. This equation permits to evaluate how the distance separating a waveguide from a ring resonator, and the ring radius, affect coupling. The effect of ring radius on the bending loss of the ring is furthermore modeled based on the measurements for silicon MRRs with different radii. These compact models for coupling and loss are subsequently used to derive the main optical properties of MRRs, such as 3-dB optical bandwidth, extinction ratio of resonance, and insertion loss, hence identifying the design space. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5–10 $\mu$ m in radius and gap sizes ranging from 120 to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects.

Automated SOFC Design Exploration

Fuel cells are a clean alternative to internal combustion engines and many experts consider them to be the future of ground-transportation. Solid oxide fuel cells are already heavily used in Japan for clean energy grid storage applications. Unlike combustion of hydrogen and oxygen that only generates heat, electrochemical reactions of hydrogen and oxygen may be separated to harness ion and electron transport for high efficiency energy conversion. We present computer automated engineering of fuel cell stack design to maximize power production and minimize energy losses. Validated cell models are applied to 3-D stack simulations, where optimization algorithms obtain better designs, faster. Each simulation conserves flow, energy, species, and charge transport using efficient sparse segregated solvers. Automated workflows and state-of-the-art search algorithms allow for fast design space exploration of fuel cell material properties, dimensions, and boundary conditions. Bibliography [1] O. R. J. G. a. J. M. V. Costa-Nunes, "Comparison of the performance of Cu–CeO 2–YSZ and Ni–YSZ composite SOFC anodes with H 2, CO, and syngas," Journal of power sources, vol. 141, no. 2, pp. 241-249, 2005. [2] F. Scholz, "Thermodynamics of electrochemical reactions," Electroanalytical Methods. Springer Berlin Heidelberg, pp. 11-31, 2010. [3] A. D. S. B. B. a. J. G. P. Le, "Validation of a Solid Oxide Fuel Cell Model on the International Energy Agency Benchmark Case with Hydrogen Fuel," Fuel Cells, vol. 15, no. 1, pp. 27-41, 2015. [4] S. G. Bratsch, "Standard electrode potentials and temperature coefficients in water at 298.15 K," Journal of Physical and Chemical Reference Data , vol. 18, no. 1, pp. 1-21, 1989. Figure 1: In solid oxide fuel cells, hydrogen fuel diffusing through the porous anode (left) reacts with oxygen ions traveling across the electrolyte membrane separator (middle) and produce electrons conducting through the solid porous cathode (right). Power is generated by flow of electrons from anode through an external circuit to the cathode (top), where they recombine with oxygen, in the air feed diffusing through the porous cathode, to repopulate membrane oxygen ions. Figure 1