Fabrication Of Thin-film Transistors Research Articles

Role of ultrathin Ti3C2Tx MXene layer for developing solution-processed high-performance low voltage metal oxide transistors

Metal oxide transistors have garnered substantial attention for their potential in low-power electronics, yet challenges remain in achieving both high performance and low operating voltages through solution-based fabrication methods. Optimizing interfacial engineering at the dielectric/semiconductor interface is of utmost importance in the fabrication of high-performance thin film transistors (TFTs). In the present article, a bilayer Ti3C2Tx-MXene/SnO2–semiconductor (Tx stands for surface termination) configuration is used to fabricate a high-performance n-type thin film transistor by using an ion-conducting Li-Al2O3 gate dielectric on a p+-Si substrate, where electrical charges are formed and modulated at the Li-Al2O3/SnO2 interface, and Ti3C2Tx-MXene nanosheets serve as the primary electrical charge channel due to their long lateral size and high mobility. A comparative characterization of two distinct TFTs is conducted, one featuring Ti3C2Tx MXene and SnO2 semiconductor layer and the other with SnO2 only. Notably, the TFT with the Ti3C2Tx MXene layer has shown a significant boost in the carrier mobility (10.6 cm2/V s), leading to remarkable improvements in the on/off ratio (1.3 × 105) and subthreshold swing (194 mV/decade), whereas the SnO2 TFT without the Ti3C2Tx MXene layer shows a mobility of 1.17 cm2/V s with 8.1 × 102 on/off ratio and 387 mV/decade subthreshold swing. This investigation provides a possible way toward the development of high-performance, low-voltage TFT fabrication with the MXene/semiconductor combination.

High-performance of low temperature solution-processed P-channel CuGaO thin film transistors

The exploration of p-type metal-oxide semiconductors (MOS) has garnered growing interest, particularly for their potential applications in next-generation optoelectronic devices, display backplanes, and low-power consumption complementary MOS (CMOS) circuits. Here, we introduced low-temperature solution-processed copper gallium oxide (CuGaO) films for p-channel thin-film transistors (TFTs). Hall Effect measurements confirmed the p-type conduction of CuGaO, revealing a conductivity and mobility of 3.76 ×10−2 S/cm and 7.89 cm2V–1s–1, respectively. The p-channel CuGaO-250 TFT demonstrated a field-effect mobility (μFE) of 1.24 cm2V–1s–1, the lowest subthreshold swing (SS) of 519 mV/dec, and an ON/OFF current ratio (ION/IOFF) of ∼104 at a low operating voltage. The notable improvement in TFT performance can be attributed to the quality of the CuGaO-250 film, a smooth surface morphology, and a reduction of interfacial traps between the semiconductor and the gate insulator. Hence, low-temperature fabrication of the p-channel CuGaO TFT holds promise for implementing metal oxide-based TFT and complementary metal oxide semiconductor (CMOS) circuits in next-generation displays.

Multi-project wafers for flexible thin-film electronics by independent foundries

Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays1–3, large-area image sensors4–6, microprocessors7–11, wearable healthcare patches12–15, digital microfluidics16,17 and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

CNT thin films based on epoxy mixtures: fabrication, electrical characteristics

The simple scaling of silicon transistors no longer ensures the advantages of high energy efficiency, driving research into nanotechnologies beyond silicon. Specifically, digital circuits based on carbon nanotube (CNT) field-effect transistors promise significant advantages in energy efficiency. However, the inability to perfectly control internal nanoscale defects and the variability of carbon nanotubes hinder the realization of very large-scale integrated systems. In this study, we investigated a novel method for fabricating transistors based on carbon nanotubes (CNTs) using epoxy mixtures, obtained the electrical properties of the transistors, and compared their microstructure and composition via the scanning electron microscopy. The carrier mobility on epoxy-based transistors was 28.87 cm²/V∙s, and the transistor switching frequency was 2.2 MHz. The samples exhibited electrical and physical stability over an extended period of time. The use of carbon nanotubes in epoxy resin as a conducting layer for transistors opens significant prospects in the field of electronics. The CNT-epoxy mixture technology allows for more flexible and rapid fabrication of thin-film transistors compared to classical methods. However, it is not appropriate to speak of a complete replacement; in this study, we present an alternative method for producing thin-film transistors, which may be of interest for specific purposes.

Solution-Processed Metal Oxide Thin-Film Transistor at Low Temperature via A Combination Strategy of H2 O2 -Inducement Technique and Infrared Irradiation Annealing.

Solution processing has emerged as a promising technique for the fabrication of oxide thin-film transistors (TFTs), offering advantages such as low cost, high throughput, and exceptional compositional control. However, achieving reasonable electrical properties typically demands high annealing temperatures in the fabrication process. In addressing this challenge, a novel combination strategy is proposed that involves integrating the H2 O2 inducement technique with infrared (IR) irradiation annealing. The study investigates the effects of precursors and IR irradiation annealing temperatures on the electrical properties of In2 O3 TFTs. It is found that H2 O2 can help accelerate the decomposition of organic residues, while IR irradiation annealing could enhance the film densification. By employing the proposed strategy, metal oxide TFTs consisting of a Zr-Al-O dielectric fabricated at 230°C and an In2 O3 channel layer fabricated at 185°C demonstrated high performance with field-effect mobility = 31.7 cm2 V-1 ·s-1 , threshold voltage = 1.3 V, subthreshold swing = 0.13 V per decade, and on-to-off current ratio = 1.1 × 105 . This work demonstrates the proposed combinational strategy is a general method to fabricate not only metal oxide semiconductorsbut also dielectrics.

Ultraflexible, High-Performance Transistors and Logic Circuits on Biocompatible Polylactic Acid (PLA) Substrate.

Wearable and implantable devices have gained significant popularity, playing a crucial role in smart healthcare and human-machine interfaces, which necessitates the development of more complex electronic devices and circuits on biocompatible flexible materials. Polylactic acid (PLA) stands out due to its biodegradability, cost-effectiveness, and low immunogenicity. In this study, we utilize a solution-based spin-coating method to produce high-quality PLA thin films, serving as substrates for the fabrication of thin-film transistors (TFTs) in which the dielectric layer material is silicon dioxide, the channel layer material is IGZO, and the gate, drain, and source material is ITO at low temperatures (<40 °C) through a shadow masking technique. The resulting PLA-TFT devices exhibited remarkable flexibility, biocompatibility, and impressive electrical characteristics, including a charge carrier mobility of 27.81 cm2/(V s), a subthreshold swing of 162.8 mV/decade, and an ON/OFF current ratio of up to 1 × 106, and maintained performance under various deformations. We successfully constructed fundamental logic gate circuits using PLA-TFTs, including AND, OR, and NOT gates, which effectively performed logical functions and demonstrated stability under diverse bending conditions. These research findings provide valuable support for future endeavors in fabricating intricate logic circuits and realizing advanced functionalities on biocompatible flexible materials.

Inkjet-printed thin-film transistors using surfactant-based transition-metal dichalcogenide nanocomposites suspended in polymeric semiconductors

Ink formulations containing a suspension of single-crystalline molybdenum disulfide (MoS2) nanosheets suspended in the polymeric semiconductor poly(3-hexylthiophene-2,5-diyl) (P3HT) were inkjet printed for the fabrication of thin-film transistors (TFT). The MoS2 nanosheets were treated with the surfactant trichloro(dodecyl)silane (DDTS) to functionalize the MoS2 surface and created a more stable suspension, reducing the agglomeration of MoS2 suspended in the P3HT solution. This ink formulation was inkjet printed onto the surface of thermal oxide coated, p+-Si wafers to form common-gate TFT device structures. The printed semiconductor formed the active region of a hybrid MoS2 suspension in P3HT of the TFTs. The field-effect mobility for the hybrid-ink TFTs was found to be three times (3×) higher compared to reference devices using pristine P3HT without the suspension. The functionalized MoS2 suspension was also found to form thinner nanosheet suspensions within the P3HT matrix that resulted in approximately 60% higher field-effect mobility compared to hybrid inks without the surfactant. The enhancement of the electrical properties of the TFTs was determined to be due to a structural change in the thin-film semiconductor. The observed current–voltage (I–V) changes were correlated to measurable structural alterations in the semiconductor thin film characterized by x-ray diffraction, atomic force microscopy, and UV–visible absorption spectroscopy.

All-Solution-Processed High-Performance MoS2 Thin-Film Transistors with a Quasi-2D Perovskite Oxide Dielectric.

Assembling solution-processed van der Waals (vdW) materials into thin films holds great promise for constructing large-scale, high-performance thin-film electronics, especially at low temperatures. While transition metal dichalcogenide thin films assembled in solution have shown potential as channel materials, fully solution-processed vdW electronics have not been achieved due to the absence of suitable dielectric materials and high-temperature processing. In this work, we report on all-solution-processedvdW thin-film transistors (TFTs) comprising molybdenum disulfides (MoS2) as the channel and Dion-Jacobson-phase perovskite oxides as the high-permittivity dielectric. The constituent layers are prepared as colloidal solutions through electrochemical exfoliation of bulk crystals, followed by sequential assembly into a semiconductor/dielectric heterostructure for TFT construction. Notably, all fabrication processes are carried out at temperatures below 250 °C. The fabricated MoS2 TFTs exhibit excellent device characteristics, including high mobility (>10 cm2 V-1 s-1) and an on/off ratio exceeding 106. Additionally, the use of a high-k dielectric allows for operation at low voltage (∼5 V) and leakage current (∼10-11 A), enabling low power consumption. Our demonstration of the low-temperature fabrication of high-performance TFTs presents a cost-effective and scalable approach for heterointegrated thin-film electronics.

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

Donor-acceptor polymeric inks with transition-metal dichalcogenide nanosheet suspensions for inkjet-printed thin-film transistors

This study investigates molybdenum disulfide (MoS2) suspension to enhance the charge transport properties of the donor-acceptor co-polymer (DA copolymers) semiconductor diketopyrrolopyrrole thieno[3,2-b]thiophene (DPPT-TT) for inkjet-printed thin-film transistor (TFT) fabrication. A mixture of MoS2 nanosheets mixed in the DA copolymer was developed and inkjet printed for the fabrication of TFT devices. The I–V measurements of the fabricated TFTs indicated that the addition of MoS2 suspension (0.5 wt%) into the polymer matrix resulted in the improvement of carrier mobility in both hole and electron transport, with an increase of 52 % and 130 %, respectively, compared to devices without the nanosheets. The improved electrical behavior was not entirely due to transport through the single crystal nanosheets. The introduced MoS2 nanosheets also induced strongly aggregated polymeric domains in the thin film compared to pristine films without the suspension, resulting in a high degree of molecular ordering within the polymeric film. The origin of the improved microstructure of DPPT-TT-based thin films was analyzed using AFM, UV–vis–NIR, and XRD systems. The structural results were shown to correlate with the electrical behavior, further demonstrating the efficacy of the MoS2 nanosheets on the enhancement of the TFT performance.

Wafer-scale organic-on-III-V monolithic heterogeneous integration for active-matrix micro-LED displays.

The organic thin-film transistor is advantageous for monolithic three-dimensional integration attributed to low temperature and facile solution processing. However, the electrical properties of solution deposited organic semiconductor channels are very sensitive to the substrate surface and processing conditions. An organic-last integration technology is developed for wafer-scale heterogeneous integration of a multi-layer organic material stack from solution onto the non-even substrate surface of a III-V micro light emitting diode plane. A via process is proposed to make the via interconnection after fabrication of the organic thin-film transistor. Low-defect uniform organic semiconductor and dielectric layers can then be formed on top to achieve high-quality interfaces. The resulting organic thin-film transistors exhibit superior performance for driving micro light emitting diode displays, in terms of milliampere driving current, and large ON/OFF current ratio approaching 1010 with excellent uniformity and reliability. Active-matrix micro light emitting diode displays are demonstrated with highest brightness of 150,000 nits and highest resolution of 254 pixels-per-inch.

Thin Film Transistors Incorporating Ultrapure Semiconducting Single-Walled Carbon Nanotubes and Green Dielectrics

Printed electronics is a burgeoning field that has received intense research interest and is beginning to experience commercial successes. Single-walled carbon nanotubes (SWNTs) are a unique and promising building block for incorporation into next generation superfast electronic devices. SWNTs have very high carrier mobilites, with band gaps compatible for integration into logic circuits. Their excellent mechanical flexibility allows for potential incorporation into flexible printed electronics, enabling fully-printed transistors and circuits with performances that support low cost, large area fabrication. Progress in incorporating SWNTs into commercial devices has been hindered by the presence of metallic SWNTs, which are produced alongside semiconducting SWNTs during synthesis, and negatively impact device performance. Fabrication of ambipolar SWNT organic thin film transistors (OTFTs) with high carrier mobilities and high on/off ratios remains particularly challenging; many examples in the literature required high temperature, expensive and energy-demanding processes.Since the initial discovery of conjugated polymer-assisted dispersion and purification of SWNTs in 2008, several polymer families have been successfully shown to selectively disperse semiconducting SWNTs. However, only a relatively small number of these supramolecular complexes have been incorporated into OTFTs. We used a novel conjugated polymer to exclusively disperse semiconducting SWNTs. The dispersal procedure requires a simple sonication and centrifugation, during which the metallic SWNTs sediment out. Solution purity was evaluated using UVVis- NIR and Raman spectroscopies. The resulting dispersions are amenable to solution processing techniques such drop casting and spin coating, allowing for the potential for large area device fabrication at room temperature. Ambipolar OTFTs were fabricated under ambient conditions using this solution and tested in both air and under inert atmosphere. The presence of excess conjugated polymer, solution deposition techniques, SWNT density, surface treatment, and post-fabrication treatment were all investigated to determine which parameters facilitated the production of OTFTs with high mobilities (>20 cm2V-1s-1), high on/off ratios (10^6-10^8), negligeble hysteresis, controlled threshold voltages, and high bias stability.[1] Protocols for sorting and dispersing ultrapure sc-SWNTs with conjugated polymers for thin-film transistor (TFT) applications have been well refined. Conventional wisdom dictates that removal of excess unbound polymer through filtration or centrifugation is necessary to produce high- erformance TFTs. However, this is time-consuming, wasteful, and resource-intensive. We challenge this paradigm and demonstrate that excess unbound polymer during semiconductor film fabrication is not necessarily detrimental to device performance.[2] With focus on further improving device performance, we look to green, compostable dielectrics to pair with SWCNTs. We report a tri-layer dielectric using poly (lactic acid) (PLA), poly(vinyl alcohol)/cellulose nanocrystals (PVAc) and toluene diisocyanate terminated poly(caprolactone) (TPCL) which we integrated into SWCNT based TFTs in a top gate bottom contact architecture. The PVA provides a high dielectric constant due to the hydroxy groups, the cellulose is used to optimize the viscosity, the TPCL layer provides a robust hydrophobic surface[3], and the PLA eliminates the interfacial charge traps present in the PVAc. This leads to a decrease in leakage currents and reduced the polarity at the dielectric/semiconductor interface. The TFTs fabricated using tri-layer dielectrics led to air stable and balanced hole and electron mobilities which was not observed for the PVAc/TPCL bilayer systems with supressed hole mobility. These TFTs were then used to study the impact of electrochemical doping on the performance of sc-SWCNT TFTs when switching from n-type, where an electrical double layer is formed, to p-type, where the TFSI anions are free to interact with the sc-SWCNTs.[4]The following presentation will focus on the engineering of sc-SWNTs based electronic devices. The choice of conjugated wrapping polymer, dielectric and processing conditions on film formation and the TFT device performance.

Room-temperature fabrication of flexible oxide TFTs by co-sputtering of IGZO and ITO

Amorphous oxide semiconductors, especially indium gallium zinc oxide (IGZO), have been widely studied and obtained significant progress in flexible thin-film transistors (TFTs) due to the high carrier mobility and low deposition temperature. However, a further annealing step is generally required to activate electrical properties and improve the device performance, which limited their applications in flexible electronics. In this study, we achieved flexible TFTs and arrays using co-sputtered IGZO and indium tin oxide (ITO) as channels deposited at room temperature without post-annealing. It was found that better transistor switching properties could be effectively achieved by regulating the sputtering power of ITO in the co-sputtered deposition. The device performance is comparable to that of the conventional oxide TFTs with high annealing temperatures (⩾300 °C), exhibiting a high saturation mobility (μ sat) of 15.3 cm2 V−1s−1, a small subthreshold swing (SS) of 0.21 V dec−1, and a very high on–off ratio (I on/off) of 1011. In addition, a 12 × 12 flexible TFT array was achieved with uniform performance owing to the low-temperature processing advantage of this technique. The flexible TFTs exhibited robust mechanical flexibility with a minimum bending radius of 5 mm and bending cycles up to 1000. Furthermore, an inverter based on co-sputtered IGZO and ITO was demonstrated with the maximum gain of 22. All these achievements based on the proposed TFTs without post-annealing process are expected to promote the applications in advanced flexible displays and large-area integrated circuits.

Mechanistic Insights into Synaptic Plasticity Behaviors of Electrolyte-Gated Flexible Transistor Devices.

Biological synaptic function simulation using flexible electronic devices based on low-dimensional semiconductor materials is an emerging and rapidly evolving research field with promising applications in brain-like computers and artificial intelligence systems. In this work, we present the fabrication of solution compatible MoS2 thin-film transistors on the ultrathin polymethyl methacrylate substrates via layer-by-layer assembly followed by a one-step transfer printing method. The MoS2 transport channel is controlled by ionic liquid gating with 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, resulting in excellent synaptic performances for emulating memory and perception synapse functions. To investigate the synaptic behaviors, we conduct a series of synaptic spike-dependent experiments and propose an advanced model that delineates the long-term plasticity and short-term plasticity with separate characteristic factors. These findings provide insights into the fundamental mechanisms of synaptic plasticity in electric double-layer devices and contribute to a better understanding of their synaptic performances. In addition, we examine the effects of bending conditions on synaptic plasticity and synaptic weights, unveiling the synergistic interplay between mechanical deformation and synaptic behaviors. Our experimental results, combined with the developed model, are in good agreement and shed light on the influence of mechanical flexibility on the synaptic properties of the devices. In summary, this study establishes a solid foundation for further development of flexible synaptic devices from both practical and theoretical perspectives.

Improving the Electrical Properties of Zinc-Tin Oxide Thin-Film Transistors by Additive using Electrohydrodynamic Jet Technology

Oxide thin-film transistors (TFTs) are important semiconductor materials for display backplanes. To fabricate flexible displays, not only display modes but also TFTs are important. Flexible TFTs are especially needed for flexible displays, and related processes need to be developed. Printing is a good choice for the new fabrication of oxide TFTs. Electrohydrodynamic (EHD) jet printing is an excellent alternative for making flexible TFTs. To improve the electrical properties of oxide TFTs using EHD jet printing, propylene monomethyl ether acetate (PGMEA) was added to a zinc-tin oxide (ZTO) formulation. EHD jet printing was performed by Taylor cone jet mode with parameters of 2.4 kV and 0.064 µL/s to obtain uniform thin films at a substrate temperature of 50oC. Much improved TFT properties were obtained, including a mobility of 7.11 cm2/V s, on-to-off current ratio of 2.8 × 106 and subthreshold slope of 1.44 V/dec for ZTO TFT with 5 wt% of PGMEA, and a mobility of 1.43 cm2/V s, on-to-off current ratio of 2.7 × 105 and subthreshold slope of 1.32 V/dec for the ZTO TFT. Almost no hysteresis behavior was observed in the oxide TFTs with added PGMEA. We report a new way to improve the electrical properties of oxide TFTs, by the simple addition of PGMEA.

Utilizing Dip-Coating to Fabricate Gate Dielectric and Semiconductor for Thin-Film Transistors

The potential applications of advanced electronic materials in large-area, printable, and flexible electronics have generated significant interest. However, creating high-performance, low-voltage thin-film transistors (TFTs) for these applications remains difficult due to a lack of advanced gate dielectric and semiconductor materials that meet both ease-of-fabrication requirements and high electrical performance. In this study, we present high-performance gate dielectric thin-films, which were fabricated using a facile solution-based technique, and then employed to realize low operating voltage organic and metal oxide semiconductor-based thin-film transistors. The high-k oxide gate dielectrics were produced via a simple dip-coating method, resulting in the formation of thin-oxide layers. These novel oxide gate dielectrics demonstrated exceptional dielectric properties, with large capacitances (up to 430 nF/ cm2), low-level leakage current densities (&lt; 3 × 10-8A/cm2 at 4 V), featureless morphology (rms roughness &lt; 0.36 nm), and high transparency (&gt; 85%). Consequently, these dip-coated gate dielectrics can be incorporated into thin-film transistors, utilizing pentacene as p-type organic semiconductors. Furthermore, by employing dip-coating, indium oxide and indium-gallium-zinc oxide can be utilized as n-type inorganic semiconductors, allowing for the fabrication of low-voltage operation and high-performance inorganic TFTs. The resulting TFTs functioned at ultralow voltages (&lt; ± 2 V) and achieved high transistor performance (hole mobility: 0.28 cm2V-1·s-1, electron mobility: ~2.0 cm2V-1·s-1 and on/off current ratio &gt;105).

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Shellac as dielectric materials in organic field-effect transistors: from silicon to paper substrates

Recent advances in the design and preparation of electroactive materials, particularly semiconducting and conductive polymers, have resulted in the creation of novel organic electronics with advanced functionality and performance competitive with that of devices made of silicon. With an increasing number of organic and printed electronics being engineered and produced at a larger scale, the environmental cost of the final organic electronic devices (life cycle, environmental impact, etc) needs to be considered. While e-waste is already a growing global problem, improving the sustainability of emerging electronics through a careful materials selection is highly desirable. In this work, we explore the use of shellac as a sustainable greener dielectric material in organic field-effect transistors. A careful examination of shellac in combination with diketopyrrolopyrrole-based semiconducting polymers was performed on rigid substrates through atomic force microscopy (AFM) and the fabrication of thin film transistors. All devices made from this green dielectric showed good performance and device characteristics. Building from this investigation, shellac was further integrated with paper substrates to fabricate paper-based thin film transistors. Thin film samples based on shellac on both silicon wafer and paper substrates were characterized by AFM to investigate solid-state morphology of shellac and selected semiconducting materials. Through careful optimization of the device architecture and processing time, device characteristics and performances on paper substrates (average charge mobilities and on/off current ratios) were comparable to those of devices prepared on silicon wafers, confirming that shellac, in combination with organic semiconducting polymers, can be an advantageous dielectric material to be used for the fabrication of greener and sustainable thin film electronics from renewable feedstocks and components.

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

Fabrication and characterization of ultra-thin ZnO based bottom gate thin film transistor for UV detection

An RF sputtered ZnO thin film was utilized in a thin film transistor (TFT) fabrication. The film was fabricated on SiO2 gate oxide that was thermally grown on Si Substrate. Few lithography steps were used to fabricate the device and device structure was proved to be a bottom gate TFT. The grown film was ultra thin of 25 nm thickness and the Si wafer was n-type. The structural and optical properties of ZnO films were investigated by Field Emission Scanning Electron Microscopy (FESEM), X-Ray Diffraction (XRD) and Photo luminance (PL) spectroscopy. The photo luminance study confirmed a high-quality absorbance in UV spectra and relatively good transmittance in the visible region. The electrical performance of the transistor was studied using Proxima B1500 and the on/off current ratio was measured to be ∼107. The ZnO bottom gate TFT is simulated using the commercial TCAD tool Silvaco ATLAS™. Later the simulated I–V characteristic of the device is compared with the experimental one and both are in fairly good agreement. Further the UV detection capability of the fabricated device was studied by using UV LED light of 365 nm wavelength. The measured value of threshold voltage was found to be 9V under dark light and 10V under UV light.