Parasitic Parameter Extraction Research Articles

Optimizing solar panel maximum power point tracking and parasitic parameter extraction in partial shading with Enhanced Slime Mold optimization

Solar energy offers several environmental, economic, and energy security advantages. Parasitic parameters and shading on solar panels can reduce efficiency. This paper presents a bio-inspired Enhanced Slime Mold (ESM) algorithm search strategy to find near-optimal power points by simulating the behaviour of slime molds in a virtual environment. In a solar panel, proposed ESM provides not only for parameter extraction but also serves as Maximum Power Point Tracking (MPPT) during Partial Shading Conditions (PSC). The proposed ESM dynamic behaviour is examined under solar irradiation and various temperature conditions. The effectiveness of proposed technique has been validated by extracting parameters from conventional polycrystalline and monocrystalline modules in the form of a 5 S–5P arrangement. In the instance of MPPT operation, the proposed ESM algorithm is compared with Ant Bee Colony and Perturb& Observe (ABC-PO) to determine its efficacy. Moreover, during extraction of unknown parameters of solar cell ESM is compared with existing optimization algorithms such as Artificial Bee Swarm Optimization (ABSO), Genetic Algorithm (GA), Covariant Matrix (CM), Ant Bee Colony (ABC), and Advanced Particle Swarm Optimization (APSO). In this connection, proposed ESM algorithm is superior to the above-mentioned algorithms due to high accuracy, a smaller number of computations, and minimum computational time.

Анализ влияния шин трассировки на результаты моделирования стандартных цифровых элементов по технологии КМОП 28 нм

In this paper, the influence of routing buses on the timing characteristics (rise/fall time and switching delay) of standard digital elements due to the manifestation of LDE and parasitic effects was studied. A set of specialized test structures to take into account such effects in layers from the first to the fourth metal was proposed. The test structures provide some of the possible cases of the relative position of the routing buses and the layout of the standard cell. Parasitic extraction and characterization of the resulting netlist were performed for each test structure. A set of netlists with parasitic parameters was characterized. It is shown that the average deviation of the temporal characteristics ranged from 1.8 to 3.9% compared to the original structure without routing buses. The largest relative deviation in switching delay is typical for the smallest load capacity, while the relative deviation of cell characteristics depends relatively weakly on the front value. On the basis of the study, recommendations were formulated for modifying the route of extraction of parasitic parameters of standard digital elements, taking into account the routing buses, in order to increase the accuracy of their modeling.

Parasitic Parameter Extraction for Calibration Standards Using an Optimization Strategy

This article presents a novel extraction method for parasitic parameters of on-wafer calibration standards using an optimization strategy. Based on the physical models of the calibration standards, the parasitic parameters of all calibration standards can be extracted using the Bayesian optimization method with a fast calculation speed and high accuracy. Compared with the conventional thru-reflect-line (TRL) extraction method, the proposed approach can work well in systems with high crosstalk. The methodology is validated through on-wafer measurements using a ground–signal–ground (GSG) probe with low crosstalk and a ground–signal (GS) probe with high crosstalk. The proposed method shows a comparable accuracy with the TRL method in the low-crosstalk case, while it has higher accuracy in the high-crosstalk scenario.

An Accurate Model for InP HEMT Small-Signal Equivalent Circuit Based on EM Simulation

A high-reliability small-signal equivalent circuit model for indium-phosphide-based high-electron-mobility transistors (InP-based HEMTs) is proposed. A de-embedding scheme for the representative structure is utilized in this model with an electromagnetic simulation approach to consider the distributed extrinsic parasitic elements. The intrinsic part of the small-signal model is directly extracted with the Y-parameter of the intrinsic two-port network. The extraction of the parametric elements was performed under different biases and three different gate widths ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 20\,\,\mu \text{m}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 30\,\,\mu \text{m}$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 50\,\,\mu \text{m}$ </tex-math></inline-formula> ), our S-parameter predictions showed good agreement with measurements in the 1–50-GHz frequency range. The proposed model performs an electromagnetic simulation of different gate-width devices, considers the devices’ distribution and radio-frequency behavior, and avoids errors caused by traditional tests’ extraction of parasitic parameters. The proposed model solves the problem that the conventional indium phosphide-based HEMT small-signal model is limited by the device topology, making the high-frequency modeling more accurate.

Accurate SiC MOSFET Chip Extraction Based on Parasitic Parameter Impact Compensation

With the growing use of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> in power electronic equipment, it is meaningful to extract precise typical waveforms and characteristics for device manufacture, converter design, and operating evaluation. Many solutions have been proposed to improve measurement precision by equipment and essential techniques. However, the measured object should also be accurately identified as the existing measurement result consisting of the expected gate-source voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and voltage drops on parasitic parameters between measuring points. This article, first, reveals the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> measurement deviation of TO-247-4 and TO-247-3 devices during the switching process and crosstalk, based on the equivalent circuit model and simulation waveforms. According to the clarification of the measured object, an improved <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> extraction method is proposed to eliminate this deviation. Voltage drops on parasitic parameters are compensated, with the help of high-precision equipment and the proven parasitic parameter extraction technique. Experiments are constructed to verify the analysis of measurement deviation and the availability of the proposed method. Comparison between various operating conditions emphasizes its necessity, especially in high-capacity and low-driving-resistor applications, contributing to characterization, operating condition monitoring, protection design, and measurement understanding of wide band-gap devices.

Parasitic parameters extraction of InP HBT only from S-parameters measured under cut-off and normal bias conditions

An improved parasitic parameters extraction method for InP heterojunction bipolar transistor (HBT) is developed. The difference between this method and previous methods is that all parasitic parameters can be extracted by relying only on the S-parameters measured under the cut-off and normal bias conditions. All the capacitance parameters in the equivalent circuit at the low-frequency cut-off can be extracted by combining the analytical closed formulas and the parameter scanning method. The intrinsic resistance Rbi is obtained indirectly by extracting the extrinsic resistance Re based on the Z-parameter method in the normal bias conditions. By de-embedding the parasitic capacitances, all the values of parasitic inductances and extrinsic resistances are obtained by the direct extraction method under the cut-off condition. The proposed method not only eliminates the critical measurement of the open-collector condition, but also greatly improves the efficiency and accuracy of parameter optimization. For different sizes and bias conditions of InP HBT devices, the excellent agreement between simulated and measured results is verified all over the frequency range of 0.4–50 GHz.

Parasitic Parameter Extraction and Identification Method for HFT Based on DC-DC Converter in EV Application

Dual active bridge (DAB) resonant converter is one of the most commonly used soft switched converters of the new electric vehicle (EV) energy system. One of the most essential parts of the DAB resonant converter, the high-frequency transformer (HFT) includes certain parasitic parameters that caused voltage and current oscillation, or ring to the DAB converter. These precise parasitic parameters of the HFT provide accurate information and are useful to the DAB converter control system design. However, they are not provided by the manufacturer. This study focuses on this prospect of information, proposing a novel parasitic parameter identification method for the HFT based on DAB converter. Moreover, a 40 kHz full-bridge resonant DAB converter prototype based on SiC MOSFETs and HFPT laboratory prototype is constructed to verify the effectiveness and feasibility of the proposed method. Simulation and experimental results verify that the proposed method is more cost-effective than the conventional way to measure via impedance (IMDP) analyzer, requires shorter simulation time than the traditional finite element analysis (FEA) method, while it is also more accurate has fast convergence than the traditional forgetting factor recursive least square (FFRLS) identification algorithm.

Implementation of a Novel Tabu Search Optimization Algorithm to Extract Parasitic Parameters of Solar Panel

The aging of PV cells reduces their electrical performance i.e., the parasitic parameters are introduced in the solar panel. The shunt resistance (RSh), series resistance (RS), photo current (IPh), diode current (Id), and diffusion constant (a1) are known as parasitic or extraction parameters. Cracks and hotspots reduce the performance of PV cells and result in poor V–I characteristics. Certain tests are carried out over a long period of time to determine the quality of solar cells; for example, 1000 h of testing is comparable to 20 years of operation. The extraction of solar parameters is important for PV modules. The Tabu Search Optimization (TSO) algorithm is a robust meta-heuristic algorithm that was employed in this study for the extraction of parasitic parameters. Particle Swarm Optimization (PSO) and a Genetic lgorithm (GA), as well as other well-known optimization methods, were used to test the proposed method’s correctness. The other approaches included the lightning search algorithm (LSA), gravitational search algorithm (GSA), and pattern search (PS). It can be concluded that the TSO approach extracts all six parameters in a reasonably short period of time. The work presented in this paper was developed and analyzed using a MATLAB-Simulink software environment.

A reliable parameter extraction method for the augmented GaN high electron mobility transistor small‐signal model

An improved GaN high electron mobility transistor (HEMT) small-signal equivalent model is proposed. To model the effects of extrinsic parameters that vary with the bias voltage, RL and Lds are added to the model. Moreover, substrate-related parameters (Rsub and Csub) are used to model the substrate effect. In order to avoid damaging the gate under high forward gate pressure conditions, an accurate parasitic parameter extraction method is proposed, which improves the reliability and validity of the parameter extraction. The S-parameters of the proposed model are in good agreement with the measured S-parameters in the range of 0.5–20.5 GHz.

Parasitic Parameters Extraction of Inp Hbt Only from S-Parameters Measured Under Cut-Off and Normal Bias Conditions

Parasitic Parameters Extraction of Inp Hbt Only from S-Parameters Measured Under Cut-Off and Normal Bias Conditions

A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

Transient Electro-Thermal Coupled Modeling of Three-Phase Power MOSFET Inverter during Load Cycles.

This study introduces an effective and efficient dynamic electro-thermal coupling analysis (ETCA) approach to explore the electro-thermal behavior of a three-phase power metal–oxide–semiconductor field-effect transistor (MOSFET) inverter for brushless direct current motor drive under natural and forced convection during a six-step operation. This coupling analysis integrates three-dimensional electromagnetic simulation for parasitic parameter extraction, simplified equivalent circuit simulation for power loss calculation, and a compact Foster thermal network model for junction temperature prediction, constructed through parametric transient computational fluid dynamics (CFD) thermal analysis. In the proposed ETCA approach, the interactions between the junction temperature and the power losses (conduction and switching losses) and between the parasitics and the switching transients and power losses are all accounted for. The proposed Foster thermal network model and ETCA approach are validated with the CFD thermal analysis and the standard ETCA approach, respectively. The analysis results demonstrate how the proposed models can be used as an effective and efficient means of analysis to characterize the system-level electro-thermal performance of a three-phase bridge inverter.

Formulae for Calculating the Resistance Parameters of Irregular Through-silicon Via

The through-silicon via (TSV) is a key technology in the three-dimensional integrated circuit, and the accuracy of its parasitic parameter extraction is the important factor of ensuring accuracy of the integrated circuit simulation. Due to the influence of the production process, the through-silicon via (TSV) is not a cylinder with a smooth surface and regular shape, and with an increase in the frequency and decrease in the size of the TSV, the irregular shape has more and more influence on the parameter extraction of the TSV. To extract the resistance parameters of an irregular TSV more rapidly and accurately, we studied the high surface ratio trapezoid and rough surface TSV and put forward the analytic expressions for calculating the resistance. The two analytic expressions reflect the change rule of resistance parameters along with the size and frequency variation of the TSV. The error of analytic expression was within 5% when compared with the simulation results, which fully satisfies the requirement of accuracy.

Extraction of SSPC Parasitic Parameters Based on Product Structure and Simulation Analysis of Resistive Load Switching Characteristics

Extraction of SSPC Parasitic Parameters Based on Product Structure and Simulation Analysis of Resistive Load Switching Characteristics

A fast small signal modeling method for GaN HEMTs

An accurate and efficient parasitic parameter extraction method is proposed for gallium nitride (GaN) high electron-mobility transistors (HEMTs). In this letter, a 19-element small signal equivalent circuit model is established to describe the characteristics of the device precisely. The simulation of the high frequency behavior is improved by introducing the series parasitic inductances into the cold pinch-off model. Through matrix transformation and equation derivation, the influence of Cpda and Cpga on parameter extraction is evaluated. It is proved that the error caused by Cpga and Cpda to the parameter extraction is less than 3%. Ignoring these influences can not only simplify parameter calculation, but also ensure its accuracy. The parasitic capacitances and parasitic inductances can be obtained simultaneously, improving the efficiency and the accuracy of parameter extraction. Meanwhile, accurate and ideal initial values are provided for the subsequent parameter optimization. Because of the accuracy of the initial values, parameter optimization eliminates the error caused by previous steps, and does not need multiple iterations, which improves the efficiency of the model parameter extraction. Compared with the traditional extraction method, the method in this letter can fast and accurately obtain the values of parameters. The simulated results show good agreement of scattering parameters up to 40 GHz.

An Accurate and Efficient Approach for High‐Frequency Transformer Parameter Extraction

Accurate parasitic parameter extraction of high-frequency transformers is one of the key techniques to efficiently design a Switched-mode power supply(SMPS). An approach to accurately and efficiently extract the parasitic parameters of high-frequency transformers is proposed. The high-frequency transformer is first decomposed into first-order RL and second-order RLC circuits according to inherent step response characteristics. Through the measured discharging pulse and damped oscillation responses of the high-frequency transformer excited by a square wave, we can extract the equivalent circuit parameters through fitting the responses with Particle swarm optimization(PSO). The equivalent circuits of the high-frequency transformer with the desired parameters are obtained for the SMPS design. We validate the effectiveness and accuracy of the proposed method with simulations and measurements.

Bias-dependent Access Resistances Extraction in 0.15 µm GaAs pHEMTs

Devices’ performance analysis and successful circuit design strongly depend on accurate large signal models. This, in turn, requires accurate small signal models. However, the reliable parasitic parameter extraction of GaAs pHEMT greatly influences the accuracy of small signal models, which also greatly influences the extraction of intrinsic elements. The access parasitic source and drain resistances, Rs and Rd, are associated with gate bias due to the two-dimensional charge control. In this work, we directly extract Rs and Rd from S-parameter measurements of the device under test (DUT) under strong inversion operating biases. The proposed method has been validated by simulation and on-wafer measurements. It shows better accuracy than existing arts in a frequency range of 0.5–40 GHz (0.5 GHz step). Furthermore, a 10-15 GHz GaAs pHEMT power amplifier (PA) is employed to further validate the developed method. The test results also validate the developed method.

Measurement and Extraction of Parasitic Parameters of Quasi-Vertical Schottky Diodes at Submillimeter Wavelengths

This letter reports on a method for extracting parasitic equivalent-circuit model parameters at submillimeter-wave frequencies. The devices investigated are quasi-vertical gallium arsenide Schottky diodes integrated on silicon. The technique utilizes measurements of coplanar waveguide-fed passive structures in the WR-2.2 band (325–500 GHz), which are fabricated on the same wafer as the diodes. These structures consist of short- and open-circuited terminations that allow direct measurement of the parasitic circuit elements associated with the device. The values of the parasitic elements obtained using this method are in agreement with the values reported in the literature for diodes of comparable geometry.

A New Method to Extract Gate Bias-Dependent Parasitic Resistances in GaAs pHEMTs

Accurate large signal GaAs pHEMT models are essential for devices’ performance analysis and microwave circuit design. This, in turn, mandates precise small signal models. However, the accuracy of small signal models strongly depends on reliable parasitic parameter extraction of GaAs pHEMT, which also greatly influences the extraction of intrinsic elements. Specifically, the parasitic source and drain resistances, R s and R d , are gate bias-dependent, due to the two-dimensional charge variations. In this paper, we propose a new method to extract R s and R d directly from S-parameter measurements of the device under test (DUT), which save excessive measurements and complicated parameter extraction. We have validated the proposed method in both simulation and on-wafer measurement, which achieves better accuracy than the existing state-of-the-art in a frequency range of 0.5–40 GHz. Furthermore, we develop a GaAs pHEMT power amplifier (PA) to further validate the developed model. The measurement results of the PA at 9–15 GHz agree with the simulation results using the proposed model.

Modeling technology of InP heterojunction bipolar transistor for THz integrated circuit

AbstractIndium phosphide (InP)‐based transistors play an important role in high‐speed circuit and high‐frequency analog circuit applications. Over the past few decades, terahertz heterojunction bipolar transistor (HBT) is increasingly developed. As a result, many reports of HBTs operating at terahertz region have flourished. Since the high‐frequency circuit design faces the challenge from the lack of precise transistor models, this paper reviews the development of high‐frequency modeling technologies of InP HBT at terahertz region. Processes in the development of small‐signal models at terahertz frequencies, precise parasitic parameters extraction method, improvements in measurement, and the de‐embedding technologies open up more opportunities for precise representation of InP HBTs. Finally, some excellent terahertz circuits based on InP HBT are reviewed.