Анализ влияния шин трассировки на результаты моделирования стандартных цифровых элементов по технологии КМОП 28 нм

Abstract

In this paper, the influence of routing buses on the timing characteristics (rise/fall time and switching delay) of standard digital elements due to the manifestation of LDE and parasitic effects was studied. A set of specialized test structures to take into account such effects in layers from the first to the fourth metal was proposed. The test structures provide some of the possible cases of the relative position of the routing buses and the layout of the standard cell. Parasitic extraction and characterization of the resulting netlist were performed for each test structure. A set of netlists with parasitic parameters was characterized. It is shown that the average deviation of the temporal characteristics ranged from 1.8 to 3.9% compared to the original structure without routing buses. The largest relative deviation in switching delay is typical for the smallest load capacity, while the relative deviation of cell characteristics depends relatively weakly on the front value. On the basis of the study, recommendations were formulated for modifying the route of extraction of parasitic parameters of standard digital elements, taking into account the routing buses, in order to increase the accuracy of their modeling.