Abstract

Fan-out wafer level packaging (FOWLP) meets the demand of integration density improvement in integrated circuit (IC) packaging. The redistribution layer (RDL) for signal transmission and power distribution in FOWLP has largely increased and leads to higher parasitic capacitance between metal lines. The parasitic capacitance is influenced by the line angles between different layers, which also will influence other parasitic parameters. In this study, the two-layer comb-like structure RDLs were designed. The equivalent circuits and their parasitic parameters were set up. The effect of line angles including 0°, 45° and 90° were studied. Then the influence of ground-signal-ground (GSG) testing structures on parasitic parameters was also investigated.

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