Extended True Single Phase Clock Research Articles

A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment

This research work presents the analysis, design, and characterization of a concept for an mm-wave divide-by-4 frequency divider utilizing an extended true single-phase clock (E-TSPC) and a TSPC divide-by-2 stage. The divider operates from 16 to 70 GHz from a 0.8-V supply with the highest power consumption of 0.35 mW. Operating frequencies up to 53 GHz were reached with a supply voltage of only 0.5 V at 0.12-mW power consumption. The self-resonance frequency of the circuit is adjustable through backgate biasing from 40 up to 70 GHz at 0.9-V supply, allowing a reduction in the required input power in this frequency range. Locking ranges up to 114% have been measured by changing only the backgate voltage. The circuit design is illustrated in detail and supported with original analysis and an explicit expression to calculate the self-oscillation frequency of the E-TSPC divider. The presented circuit was fabricated on a 22-nm fully depleted silicon-on-isolator complementary metal–oxide–semiconductor (CMOS) technology and occupies an active area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.4 ~\mu \text{m}^{2}$ </tex-math></inline-formula> . The circuit requires the lowest power consumption and area among state-of-the-art RF frequency dividers, while it demonstrates the second widest adjustable operating frequency range and the second highest self-resonance frequency for CMOS D-flip-flop frequency dividers.

A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

Design of a low-power 12.5Gb/s 1:10 demultiplexer in 0.18μm CMOS*

A low-power 12.5Gb/s 1:10 Demultiplexer (DEMUX) without inductors is designed in 0.18μm CMOS (Complementary metal oxide semiconductor) process. The 1:10 DEMUX includes a high-speed 1:2 DEMUX, two serial low-speed 1:5 DEMUX, a 5 frequency divider and so on. The latch of the high-speed 1:2 DEMUX adopts the CML (Current Mode Logic) structure. The rest of the triggers all use E-TSPC(Extended True Single Phase Clock)structure. In the design of the 5 frequency divider, the logic gate circuit is embedded in flip-flop to improve the work frequency. The post simulated result shows that when the data rate of the input pseudorandom is 12.5Gb/s and the clock frequency is 6.25GHz at a supply voltage of 1.8V, this1:10 DEMUX can work well and the eye diagram of output data is clear. The output swing is 400mV on an external 50 Ohm load and the total power dissipation is 200mW. The die size is 0.64×0.57mm2.

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

Low Voltage and High Speed Dual-Modulus Prescaler with E-TSPC Technology for Frequency Synthesizer

In this paper, a new extended true-single-phase-clock (E-TSPC) based divide-by-2/3 prescaler is proposed for low supply voltage and low power consumption applications. By using pass transistor logic and changing the logic gates, the critical path between the E-TSPC flip-flops has been reduced. Prescaler is designed by Cadence in chartered 0.18 µm CMOS process. Simulation results show that proposed dual-modulus prescaler can work up to 3.9 GHz under 0.9 V supply voltage with 226 µW power consumption and it is suitable for low power and high speed frequency synthesizer in wireless communication system.

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6dBc/Hz at 1MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1mW. The chip with an area of 1.048×1.076mm2 is fabricated in a TSMC 0.18μm CMOS 1P6M technology process.

Design of Low Noise 10 GHz divide by 16…511 Frequency Divider

In this paper design and simulation of a 10 GHz, divide‑by‑16…511 programmable frequency divider based on ETSPC and TSPC logic flip-flops in 65 nm CMOS are presented. Main blocks of the divider are three-stage dual modulus divide by 2/3 divider chain, 6-bit counter, jitter removal and synchronisation flip-flops. Extended True Single Phase Clock (ETSPC) logic is used for 2/3 dividers to achieve high input frequency and low power and TSPC logic is used for 6-bit counter. Simulation of the divider was made using Cadence software. Divider’s operation frequency is up to 10 GHz. Resulted phase noise is -143.7 dBc/Hz at 1 kHz offset from output frequency and power dissipation is 29.35 mW when input frequency is 10 GHz, division ratio is set to 23, supply voltage 1.2 V. The main application of such divider is as feedback divider in frequency synthesizer for wireless communication systems.DOI: http://dx.doi.org/10.5755/j01.eee.19.6.4570

Power Optimized Divide-By-2/3 Counter Based Clock Design Using Multiplexer

This paper proposes a advanced method of extended true-single-phase-clock (E-TSPC) based divide- by-2/3 counter design for providing low supply voltage and low power consumption. The counting logic and the mode selection control can be desingned by the help of single transistor using wired OR method. The proposed method mainly focus on for saving power consumption and it reduces the critical path between the E-TSPC flip flops (FFs) for improving the operating frequency of the counter. E-TSPC will reduce the design time, Layout area, in power-delay-product and increase the operation speed can be achieved by the proposed design and expected 1.0 to 2.0% of power reduction. The E-TSPC Prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique

An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired or scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (FFs). Since the number of transistor stacking between the power rails is kept at merely two, the proposed design is sustainable to low VDD operations (531 MHz at 0.6 V VDD) for the power saving purpose. Simulation results show that compared with two classic E-TSPC based designs in 0.18 m process technology, as much as 16.4% in operation speed and 39% in power-delay-product can be achieved by the proposed design.

Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a chartered 0.18 ¿m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.

An E-TSPC Divide-by-2 Circuit With Forward Body Biasing in 0.25 $\mu$m CMOS

A forward body biasing (FBB) technique is employed by an extended true-single-phase-clock (E-TSPC) divide-by-2 circuit in 0.25 mu m CMOS for an efficient on-chip control of power and speed. By applying the forward body bias voltage of 0.4 V, the maximum operating frequency is improved by 78% while the current dissipation is increased only by 21%. As a result, the divider figure-of-merit is improved by 46%. The phase noise however is not significantly affected by the forward body biasing. We believe that the FBB technique can be an efficient means for on-chip scaling of speed and power in E-TSPC RF frequency divider circuits.

Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications

Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design

New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 /spl mu/m CMOS process is fully depicted. This prescaler, according to simulations, reaches a maximum 2.19-GHz operation rate at 5 V with a 46 mW power consumption. This new approach is also compared with a previous design (implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate) and with other recently published circuits.

A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)

The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, data-precharged, and NMOS-like CMOS blocks. The composition rules, as well as the CMOS blocks, are described and discussed. The experimental results of the complete dual-modulus prescaler, implemented in a 0.8 /spl mu/m CMOS process, show a maximum 1.59 GHz operation rate at 5 V with 12.8 mW power consumption. They are compared with the results from other recent implementations showing that the proposed E-TSPC circuit can reach high speed with both smaller area and lower power consumption.