Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design

Abstract

New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 /spl mu/m CMOS process is fully depicted. This prescaler, according to simulations, reaches a maximum 2.19-GHz operation rate at 5 V with a 46 mW power consumption. This new approach is also compared with a previous design (implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate) and with other recently published circuits.