The use of extended TSPC CMOS structures to build circuits with doubled input/output data throughput

Abstract

New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional TSPC, are presented. These structures are formed by the connection of proper data paths and allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are reported briefly, and, to illustrate more complex applications, the design of a dual-modulus prescaler (divide by 128/129) in a 0.8 /spl mu/m CMOS process is fully depicted. The prescaler, according to simulations, reaches a maximum 2.19 GHz operation rate at 5 V with the 46 mW power consumption. The prescaler is compared with a preview design, implemented with the E-TSPC technique and attaining a 1.59 GHz operation rate, and with other recently published circuits.