E-TSPC: Extended True Single-Phase-Clock CMOS circuit technique

Abstract

The Extended True Single-Phase-Clock (E-TSPC), an extension of the TSPC CMOS circuit technique, is proposed and analysed. This technique consists of a set of composition rules to build CMOS single-phase circuits. The composition rules are provided to avoid race problems and to preserve data during the holding phases. The used CMOS blocks are the conventional static CMOS logic, n/p dynamic logic, n/p latch, data precharged, and the new N-MOS like blocks. Design results show that the E-TSPC can achieve 70% speed improvements, comparing with conventional TSPC techniques, and large power and area savings. A complete dual-modulus prescaler (divide-by-128/129) was implemented in a 0.8µm CMOS process, and a 1.61GHz rate was achieved with a 14.2mW power consumption.